From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34564) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTD9-0007KJ-TV for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:50:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbTD5-00022U-QH for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:50:19 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:14994) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTD5-00022F-L2 for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:50:15 -0400 From: Leon Alrae Date: Mon, 14 Sep 2015 13:49:54 +0100 Message-ID: <1442234994-15841-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH] target-mips: add missing restriction in DAUI instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net rs cannot be the zero register, Reserved Instruction exception must be signalled for this case. Signed-off-by: Leon Alrae --- target-mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 7fb7c01..a8fd4a3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19512,7 +19512,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); - if (rt != 0) { + if (rs == 0) { + generate_exception(ctx, EXCP_RI); + } else if (rt != 0) { TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); -- 2.1.0