From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36454) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTL9-0001yu-MK for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbTL6-0005Yk-G7 for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:35 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:48170) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTL6-0005YV-AS for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:32 -0400 From: Leon Alrae Date: Mon, 14 Sep 2015 13:58:22 +0100 Message-ID: <1442235504-15910-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 0/2] target-mips: non-enabled interrupts can wake up the CPU in R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net MIPS Release 6 requires that the CPU blocked on WAIT instruction can be woken up by an interrupt, even if interrupts are not enabled. First patch does not contain any functional change, it just moves the "are interrupts enabled?" part into separate cpu_mips_hw_interrupts_enabled() function. Second patch allows the R6 CPU to resume the execution regardless of cpu_mips_hw_interrupts_enabled(). Leon Alrae (2): target-mips: move the test for enabled interrupts to a separate function target-mips: implement the CPU wake-up on non-enabled interrupts in R6 target-mips/cpu.c | 9 ++++++--- target-mips/cpu.h | 29 +++++++++++++++-------------- target-mips/helper.c | 3 ++- 3 files changed, 23 insertions(+), 18 deletions(-) -- 2.1.0