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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v16 25/35] target-tilegx: Handle bitfield instructions
Date: Mon, 14 Sep 2015 15:43:32 -0700	[thread overview]
Message-ID: <1442270622-8955-26-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1442270622-8955-1-git-send-email-rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-tilegx/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index cb21c14..9604320 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1125,13 +1125,87 @@ static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
                                  unsigned dest, unsigned srca,
                                  unsigned bfs, unsigned bfe)
 {
+    TCGv tdest = dest_gr(dc, dest);
+    TCGv tsrca = load_gr(dc, srca);
+    TCGv tsrcd;
+    int len;
     const char *mnemonic;
 
+    /* The bitfield is either between E and S inclusive,
+       or up from S and down from E inclusive.  */
+    if (bfs <= bfe) {
+        len = bfe - bfs + 1;
+    } else {
+        len = (64 - bfs) + (bfe + 1);
+    }
+
     switch (ext) {
     case BFEXTU_BF_OPCODE_X0:
+        if (bfs == 0 && bfe == 7) {
+            tcg_gen_ext8u_tl(tdest, tsrca);
+        } else if (bfs == 0 && bfe == 15) {
+            tcg_gen_ext16u_tl(tdest, tsrca);
+        } else if (bfs == 0 && bfe == 31) {
+            tcg_gen_ext32u_tl(tdest, tsrca);
+        } else {
+            int rol = 63 - bfe;
+            if (bfs <= bfe) {
+                tcg_gen_shli_tl(tdest, tsrca, rol);
+            } else {
+                tcg_gen_rotli_tl(tdest, tsrca, rol);
+            }
+            tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
+        }
+        mnemonic = "bfextu";
+        break;
+
     case BFEXTS_BF_OPCODE_X0:
+        if (bfs == 0 && bfe == 7) {
+            tcg_gen_ext8s_tl(tdest, tsrca);
+        } else if (bfs == 0 && bfe == 15) {
+            tcg_gen_ext16s_tl(tdest, tsrca);
+        } else if (bfs == 0 && bfe == 31) {
+            tcg_gen_ext32s_tl(tdest, tsrca);
+        } else {
+            int rol = 63 - bfe;
+            if (bfs <= bfe) {
+                tcg_gen_shli_tl(tdest, tsrca, rol);
+            } else {
+                tcg_gen_rotli_tl(tdest, tsrca, rol);
+            }
+            tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
+        }
+        mnemonic = "bfexts";
+        break;
+
     case BFINS_BF_OPCODE_X0:
+        tsrcd = load_gr(dc, dest);
+        if (bfs <= bfe) {
+            tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
+        } else {
+            tcg_gen_rotri_tl(tdest, tsrcd, bfs);
+            tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
+            tcg_gen_rotli_tl(tdest, tdest, bfs);
+        }
+        mnemonic = "bfins";
+        break;
+
     case MM_BF_OPCODE_X0:
+        tsrcd = load_gr(dc, dest);
+        if (bfs == 0) {
+            tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
+        } else {
+            uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
+            TCGv tmp = tcg_const_tl(mask);
+
+            tcg_gen_and_tl(tdest, tsrcd, tmp);
+            tcg_gen_andc_tl(tmp, tsrca, tmp);
+            tcg_gen_or_tl(tdest, tdest, tmp);
+            tcg_temp_free(tmp);
+        }
+        mnemonic = "mm";
+        break;
+
     default:
         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     }
-- 
2.4.3

  parent reply	other threads:[~2015-09-14 22:44 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-14 22:43 [Qemu-devel] [PATCH v16 00/35] TileGX basic instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 01/35] linux-user: tilegx: Add architecture related features Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 02/35] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-09-15 10:45   ` Peter Maydell
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 03/35] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 04/35] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 05/35] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 06/35] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 07/35] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 08/35] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 09/35] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 10/35] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 11/35] target-tilegx: Framework for decoding bundles Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 12/35] target-tilegx: Generate SEGV properly Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 13/35] target-tilegx: Add TILE-Gx building files Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 14/35] target-tilegx: Handle simple logical operations Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 15/35] target-tilegx: Handle arithmetic instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 16/35] host-utils: Add revbit functions Richard Henderson
2015-09-15 10:00   ` Peter Maydell
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 17/35] target-arm: Use new " Richard Henderson
2015-09-15 10:01   ` Peter Maydell
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 18/35] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-09-15 10:02   ` Peter Maydell
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 19/35] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 20/35] target-tilegx: Handle post-increment " Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 21/35] target-tilegx: Handle unconditional jump instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 22/35] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 23/35] target-tilegx: Handle comparison instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 24/35] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-09-14 22:43 ` Richard Henderson [this message]
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 26/35] target-tilegx: Handle shift instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 27/35] target-tilegx: Handle conditional move instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 28/35] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 29/35] target-tilegx: Handle mask instructions Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 30/35] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 31/35] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 32/35] target-tilegx: Handle atomic instructions Richard Henderson
2015-09-15 10:46   ` Peter Maydell
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 33/35] target-tilegx: Handle v4int_l/h Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 34/35] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-09-14 22:43 ` [Qemu-devel] [PATCH v16 35/35] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-09-15 11:03   ` Peter Maydell
2015-09-15 11:04 ` [Qemu-devel] [PATCH v16 00/35] TileGX basic instructions Peter Maydell

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