From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, gang.chen.5i5j@gmail.com
Subject: [Qemu-devel] [PULL 15/35] target-tilegx: Handle arithmetic instructions
Date: Tue, 15 Sep 2015 08:03:53 -0700 [thread overview]
Message-ID: <1442329453-16260-16-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1442329453-16260-1-git-send-email-rth@twiddle.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 90 insertions(+), 6 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 68c7db2..6b5de55 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -160,6 +160,23 @@ static TCGv dest_gr(DisasContext *dc, unsigned reg)
return dc->wb[n].val = tcg_temp_new_i64();
}
+static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
+ void (*operate)(TCGv, TCGv, TCGv))
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ tcg_gen_ext32s_tl(t0, tsrcb);
+ operate(tdest, tdest, t0);
+
+ tcg_gen_movi_tl(t0, 0x7fffffff);
+ tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
+ tcg_gen_movi_tl(t0, -0x80000000LL);
+ tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
+
+ tcg_temp_free(t0);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -277,15 +294,24 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
switch (opext) {
case OE_RRR(ADDXSC, 0, X0):
case OE_RRR(ADDXSC, 0, X1):
+ gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
+ mnemonic = "addxsc";
+ break;
case OE_RRR(ADDX, 0, X0):
case OE_RRR(ADDX, 0, X1):
case OE_RRR(ADDX, 0, Y0):
case OE_RRR(ADDX, 0, Y1):
+ tcg_gen_add_tl(tdest, tsrca, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addx";
+ break;
case OE_RRR(ADD, 0, X0):
case OE_RRR(ADD, 0, X1):
case OE_RRR(ADD, 0, Y0):
case OE_RRR(ADD, 0, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_add_tl(tdest, tsrca, tsrcb);
+ mnemonic = "add";
+ break;
case OE_RRR(AND, 0, X0):
case OE_RRR(AND, 0, X1):
case OE_RRR(AND, 5, Y0):
@@ -422,30 +448,58 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
case OE_RRR(ROTL, 6, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SHL1ADDX, 0, X0):
case OE_RRR(SHL1ADDX, 0, X1):
case OE_RRR(SHL1ADDX, 7, Y0):
case OE_RRR(SHL1ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 1);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl1addx";
+ break;
case OE_RRR(SHL1ADD, 0, X0):
case OE_RRR(SHL1ADD, 0, X1):
case OE_RRR(SHL1ADD, 1, Y0):
case OE_RRR(SHL1ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 1);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl1add";
+ break;
case OE_RRR(SHL2ADDX, 0, X0):
case OE_RRR(SHL2ADDX, 0, X1):
case OE_RRR(SHL2ADDX, 7, Y0):
case OE_RRR(SHL2ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 2);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl2addx";
+ break;
case OE_RRR(SHL2ADD, 0, X0):
case OE_RRR(SHL2ADD, 0, X1):
case OE_RRR(SHL2ADD, 1, Y0):
case OE_RRR(SHL2ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 2);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl2add";
+ break;
case OE_RRR(SHL3ADDX, 0, X0):
case OE_RRR(SHL3ADDX, 0, X1):
case OE_RRR(SHL3ADDX, 7, Y0):
case OE_RRR(SHL3ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 3);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl3addx";
+ break;
case OE_RRR(SHL3ADD, 0, X0):
case OE_RRR(SHL3ADD, 0, X1):
case OE_RRR(SHL3ADD, 1, Y0):
case OE_RRR(SHL3ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 3);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl3add";
+ break;
case OE_RRR(SHLX, 0, X0):
case OE_RRR(SHLX, 0, X1):
case OE_RRR(SHL, 0, X0):
@@ -471,16 +525,27 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(STNT4, 0, X1):
case OE_RRR(STNT, 0, X1):
case OE_RRR(ST, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SUBXSC, 0, X0):
case OE_RRR(SUBXSC, 0, X1):
+ gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
+ mnemonic = "subxsc";
+ break;
case OE_RRR(SUBX, 0, X0):
case OE_RRR(SUBX, 0, X1):
case OE_RRR(SUBX, 0, Y0):
case OE_RRR(SUBX, 0, Y1):
+ tcg_gen_sub_tl(tdest, tsrca, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "subx";
+ break;
case OE_RRR(SUB, 0, X0):
case OE_RRR(SUB, 0, X1):
case OE_RRR(SUB, 0, Y0):
case OE_RRR(SUB, 0, Y1):
+ tcg_gen_sub_tl(tdest, tsrca, tsrcb);
+ mnemonic = "sub";
+ break;
case OE_RRR(V1ADDUC, 0, X0):
case OE_RRR(V1ADDUC, 0, X1):
case OE_RRR(V1ADD, 0, X0):
@@ -640,11 +705,21 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
const char *mnemonic;
switch (opext) {
+ case OE(ADDI_OPCODE_Y0, 0, Y0):
+ case OE(ADDI_OPCODE_Y1, 0, Y1):
case OE_IM(ADDI, X0):
case OE_IM(ADDI, X1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ mnemonic = "addi";
+ break;
+ case OE(ADDXI_OPCODE_Y0, 0, Y0):
+ case OE(ADDXI_OPCODE_Y1, 0, Y1):
case OE_IM(ADDXI, X0):
case OE_IM(ADDXI, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addxi";
+ break;
case OE(ANDI_OPCODE_Y0, 0, Y0):
case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE_IM(ANDI, X0):
@@ -752,21 +827,30 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(V2SHRSI, X1):
case OE_SH(V2SHRUI, X0):
case OE_SH(V2SHRUI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
- case OE(ADDI_OPCODE_Y0, 0, Y0):
- case OE(ADDI_OPCODE_Y1, 0, Y1):
case OE(ADDLI_OPCODE_X0, 0, X0):
case OE(ADDLI_OPCODE_X1, 0, X1):
- case OE(ADDXI_OPCODE_Y0, 0, Y0):
- case OE(ADDXI_OPCODE_Y1, 0, Y1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ mnemonic = "addli";
+ break;
case OE(ADDXLI_OPCODE_X0, 0, X0):
case OE(ADDXLI_OPCODE_X1, 0, X1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addxli";
+ break;
case OE(CMPEQI_OPCODE_Y0, 0, Y0):
case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(SHL16INSLI_OPCODE_X0, 0, X0):
case OE(SHL16INSLI_OPCODE_X1, 0, X1):
+ tcg_gen_shli_tl(tdest, tsrca, 16);
+ tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
+ mnemonic = "shl16insli";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
--
2.4.3
next prev parent reply other threads:[~2015-09-15 15:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-15 15:03 [Qemu-devel] [PULL 00/35] TileGX basic instructions Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 01/35] linux-user: tilegx: Add architecture related features Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 02/35] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 03/35] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 04/35] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 05/35] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 06/35] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 07/35] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 08/35] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 09/35] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 10/35] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 11/35] target-tilegx: Framework for decoding bundles Richard Henderson
2015-09-16 15:36 ` Chen Gang
2015-09-15 15:03 ` [Qemu-devel] [PULL 12/35] target-tilegx: Generate SEGV properly Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 13/35] target-tilegx: Add TILE-Gx building files Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 14/35] target-tilegx: Handle simple logical operations Richard Henderson
2015-09-15 15:03 ` Richard Henderson [this message]
2015-09-15 15:03 ` [Qemu-devel] [PULL 16/35] host-utils: Add revbit functions Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 17/35] target-arm: Use new " Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 18/35] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 19/35] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 20/35] target-tilegx: Handle post-increment " Richard Henderson
2015-09-15 15:03 ` [Qemu-devel] [PULL 21/35] target-tilegx: Handle unconditional jump instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 22/35] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 23/35] target-tilegx: Handle comparison instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 24/35] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 25/35] target-tilegx: Handle bitfield instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 26/35] target-tilegx: Handle shift instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 27/35] target-tilegx: Handle conditional move instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 28/35] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 29/35] target-tilegx: Handle mask instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 30/35] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 31/35] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 32/35] target-tilegx: Handle atomic instructions Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 33/35] target-tilegx: Handle v4int_l/h Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 34/35] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-09-15 15:04 ` [Qemu-devel] [PULL 35/35] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-09-16 15:28 ` Chen Gang
2015-09-16 14:50 ` [Qemu-devel] [PULL 00/35] TileGX basic instructions Peter Maydell
2015-09-16 15:20 ` Chen Gang
2015-09-16 22:36 ` Chen Gang
2015-09-27 11:48 ` Chen Gang
2015-09-28 13:58 ` Chen Gang
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