From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55065) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zc9Vi-0004sh-3z for qemu-devel@nongnu.org; Wed, 16 Sep 2015 06:00:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zc9Vc-0001E0-0l for qemu-devel@nongnu.org; Wed, 16 Sep 2015 06:00:17 -0400 Received: from mailhub.sw.ru ([195.214.232.25]:21854 helo=relay.sw.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zc9Vb-00019g-KF for qemu-devel@nongnu.org; Wed, 16 Sep 2015 06:00:11 -0400 From: "Denis V. Lunev" Date: Wed, 16 Sep 2015 12:59:43 +0300 Message-Id: <1442397584-16698-3-git-send-email-den@openvz.org> In-Reply-To: <1442397584-16698-1-git-send-email-den@openvz.org> References: <1442397584-16698-1-git-send-email-den@openvz.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 2/3] target-i386/kvm: set Hyper-V features cpuid bit HV_X64_MSR_VP_INDEX_AVAILABLE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Marcelo Tosatti , qemu-devel@nongnu.org, Paolo Bonzini , Andrey Smetanin , "Denis V. Lunev" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson From: Andrey Smetanin Hyper-V features bit HV_X64_MSR_VP_INDEX_AVAILABLE value is based on cpu option "hv-vpindex" and kernel support of HV_X64_MSR_VP_INDEX. Signed-off-by: Andrey Smetanin Signed-off-by: Denis V. Lunev CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost CC: "Andreas F=C3=A4rber" CC: Marcelo Tosatti --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 1 + target-i386/kvm.c | 11 ++++++++++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 3789a2f..85b9bd2 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -90,6 +90,7 @@ typedef struct X86CPU { int hyperv_spinlock_attempts; bool hyperv_time; bool hyperv_reset; + bool hyperv_vpindex; bool check_cpuid; bool enforce_cpuid; bool expose_kvm; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 21828ad..86dc8fa 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3122,6 +3122,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false), DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false), DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false), + DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 37e82fb..5bf2c51 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -81,6 +81,7 @@ static bool has_msr_hv_hypercall; static bool has_msr_hv_vapic; static bool has_msr_hv_tsc; static bool has_msr_hv_reset; +static bool has_msr_hv_vpindex; static bool has_msr_mtrr; static bool has_msr_xss; =20 @@ -459,7 +460,8 @@ static bool hyperv_enabled(X86CPU *cpu) (hyperv_hypercall_available(cpu) || cpu->hyperv_time || cpu->hyperv_relaxed_timing || - cpu->hyperv_reset); + cpu->hyperv_reset || + cpu->hyperv_vpindex); } =20 static Error *invtsc_mig_blocker; @@ -528,6 +530,9 @@ int kvm_arch_init_vcpu(CPUState *cs) if (cpu->hyperv_reset && has_msr_hv_reset) { c->eax |=3D HV_X64_MSR_RESET_AVAILABLE; } + if (cpu->hyperv_vpindex && has_msr_hv_vpindex) { + c->eax |=3D HV_X64_MSR_VP_INDEX_AVAILABLE; + } c =3D &cpuid_data.entries[cpuid_i++]; c->function =3D HYPERV_CPUID_ENLIGHTMENT_INFO; if (cpu->hyperv_relaxed_timing) { @@ -852,6 +857,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hv_reset =3D true; continue; } + if (kvm_msr_list->indices[i] =3D=3D HV_X64_MSR_VP_INDEX)= { + has_msr_hv_vpindex =3D true; + continue; + } } } =20 --=20 2.1.4