From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42869) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvh-0005c6-3t for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:15:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZdIvc-0002ww-4c for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:15:53 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:34518) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvb-0002wQ-VP for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:15:48 -0400 Received: by padhy16 with SMTP id hy16so75839386pad.1 for ; Sat, 19 Sep 2015 07:15:47 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 19 Sep 2015 07:15:22 -0700 Message-Id: <1442672127-26223-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> References: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH RFC 3/8] target-arm: Add support for S2 page-table protection bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 33be8c2..6f0ed51 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6008,6 +6008,38 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } +/* Translate S2 section/page access permissions to protection flags + * + * @env: CPUARMState + * @ap: The 2-bit simple AP (AP[2:1]) + * @xn: XN (execute-never) bit + */ +static int get_S2prot(CPUARMState *env, int ap, int xn) +{ + int prot_rw; + + switch (ap) { + default: + case 0: + prot_rw = 0; + break; + case 1: + prot_rw = PAGE_READ | PAGE_EXEC; + break; + case 2: + prot_rw = PAGE_WRITE; + break; + case 3: + prot_rw = PAGE_READ | PAGE_EXEC | PAGE_WRITE; + break; + } + + if (xn) { + prot_rw &= ~PAGE_EXEC; + } + return prot_rw; +} + /* Translate section/page access permissions to protection flags * * @env: CPUARMState @@ -6617,6 +6649,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Extract attributes from the descriptor and merge with table attrs */ attrs = extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx == ARMMMUIdx_S2NS) { + /* The following extractions do not apply to S2. */ + break; + } attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 @@ -6638,11 +6675,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } ap = extract32(attrs, 4, 2); - ns = extract32(attrs, 3, 1); xn = extract32(attrs, 12, 1); - pxn = extract32(attrs, 11, 1); - *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); + if (mmu_idx == ARMMMUIdx_S2NS) { + ns = true; + *prot = get_S2prot(env, ap, xn); + } else { + ns = extract32(attrs, 3, 1); + pxn = extract32(attrs, 11, 1); + *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); + } fault_type = permission_fault; if (!(*prot & (1 << access_type))) { -- 1.9.1