From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvr-0005yC-LF for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZdIvq-00035w-Ak for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:03 -0400 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]:33379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvq-00035m-2g for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:02 -0400 Received: by pacex6 with SMTP id ex6so75922540pac.0 for ; Sat, 19 Sep 2015 07:16:01 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 19 Sep 2015 07:15:25 -0700 Message-Id: <1442672127-26223-7-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> References: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH RFC 6/8] target-arm: Add S2 translation support for S1 PTW List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Add support for applying S2 translation to S1 page-table walks. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-- target-arm/op_helper.c | 4 ++-- 2 files changed, 50 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6eb903b..eac1a25 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -19,6 +19,12 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi); +static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, uint32_t *fsr, + ARMMMUFaultInfo *fi); + /* Definitions for the PMCCNTR and PMCR registers */ #define PMCRD 0x8 #define PMCRC 0x4 @@ -6146,6 +6152,32 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, return true; } +/* Translate a S1 pagetable walk through S2 if needed. */ +static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + hwaddr addr, MemTxAttrs txattrs, + uint32_t *fsr, + ARMMMUFaultInfo *fi) +{ + if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && + !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + target_ulong s2size; + hwaddr s2pa; + int s2prot; + int ret; + + ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, + &txattrs, &s2prot, &s2size, fsr, fi); + if (ret) { + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + return ~0; + } + addr = s2pa; + } + return addr; +} + /* All loads done in the course of a page table walk go through here. * TODO: rather than ignoring errors from physical memory reads (which * are external aborts in ARM terminology) we should propagate this @@ -6161,11 +6193,19 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure) return address_space_ldl(cs->as, addr, attrs, NULL); } -static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure) +static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, uint32_t *fsr, + ARMMMUFaultInfo *fi) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; attrs.secure = is_secure; + addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); + if (fi->s1ptw) { + return 0; + } return address_space_ldq(cs->as, addr, attrs, NULL); } @@ -6625,7 +6665,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr |= (address >> (granule_sz * (4 - level))) & descmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(cs, descaddr, !nstable); + descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); + if (fi->s1ptw) { + goto do_fault; + } + if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { /* Invalid, or the Reserved level 3 encoding */ @@ -6708,6 +6752,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, do_fault: /* Long-descriptor format IFSR/DFSR value */ *fsr = (1 << 9) | (fault_type << 2) | level; + /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ + fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); return true; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 7ff3c61..d4715f4 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -104,10 +104,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, * information; this is always true for exceptions reported to EL1. */ if (is_write == 2) { - syn = syn_insn_abort(same_el, 0, 0, syn); + syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn); exc = EXCP_PREFETCH_ABORT; } else { - syn = syn_data_abort(same_el, 0, 0, 0, is_write == 1, syn); + syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn); if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { fsr |= (1 << 11); } -- 1.9.1