From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvv-00064s-4N for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZdIvu-00037s-7y for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:06 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:33382) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZdIvu-00037O-23 for qemu-devel@nongnu.org; Sat, 19 Sep 2015 10:16:06 -0400 Received: by pacex6 with SMTP id ex6so75923408pac.0 for ; Sat, 19 Sep 2015 07:16:05 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 19 Sep 2015 07:15:26 -0700 Message-Id: <1442672127-26223-8-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> References: <1442672127-26223-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH RFC 7/8] target-arm: Route S2 MMU faults to EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/op_helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index d4715f4..2ccd1c9 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -90,13 +90,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t syn, exc; - bool same_el = (arm_current_el(env) != 0); + unsigned int target_el; + bool same_el; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } + target_el = exception_target_el(env); + if (fi.stage2) { + target_el = 2; + } + same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */ syn = fsr & ~(1 << 9); @@ -116,7 +122,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, env->exception.vaddress = addr; env->exception.fsr = fsr; - raise_exception(env, exc, syn, exception_target_el(env)); + raise_exception(env, exc, syn, target_el); } } #endif -- 1.9.1