From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38761) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZeU8P-0005CQ-T3 for qemu-devel@nongnu.org; Tue, 22 Sep 2015 16:25:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZeU8M-00018M-TQ for qemu-devel@nongnu.org; Tue, 22 Sep 2015 16:25:53 -0400 Received: from mail-ig0-x235.google.com ([2607:f8b0:4001:c05::235]:35563) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZeU8M-000185-G4 for qemu-devel@nongnu.org; Tue, 22 Sep 2015 16:25:50 -0400 Received: by igbkq10 with SMTP id kq10so88160447igb.0 for ; Tue, 22 Sep 2015 13:25:50 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 22 Sep 2015 13:24:50 -0700 Message-Id: <1442953507-4074-9-git-send-email-rth@twiddle.net> In-Reply-To: <1442953507-4074-1-git-send-email-rth@twiddle.net> References: <1442953507-4074-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 08/25] target-mips: Add delayed branch state to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, aurelien@aurel32.net Reviewed-by: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-mips/cpu.h | 1 + target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index ed7d86d..fd23832 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -132,6 +132,7 @@ struct CPUMIPSFPUContext { }; #define NB_MMU_MODES 3 +#define TARGET_INSN_START_EXTRA_WORDS 2 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { diff --git a/target-mips/translate.c b/target-mips/translate.c index 57e826d..30d7d46 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19562,6 +19562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.CP0_Config1 = env->CP0_Config1; ctx.tb = tb; ctx.bstate = BS_NONE; + ctx.btarget = 0; ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3; @@ -19603,7 +19604,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(ctx.pc); + tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget); num_insns++; if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { -- 2.4.3