From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
dbarboza@ventanamicro.com
Subject: Re: [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn
Date: Sat, 26 Apr 2025 00:28:46 +0200 [thread overview]
Message-ID: <14432b9f-d1a9-444c-9372-90541cf1de04@linaro.org> (raw)
In-Reply-To: <20250425152311.804338-2-richard.henderson@linaro.org>
On 25/4/25 17:23, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 3 +-
> target/riscv/csr.c | 226 +++++++++++++++++++++++----------------------
> 2 files changed, 118 insertions(+), 111 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 167909c89b..4d41a66d72 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -841,7 +841,8 @@ typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
> typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
> target_ulong *ret_value);
> typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
> - target_ulong new_value);
> + target_ulong new_value,
> + uintptr_t ra);
> typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
> target_ulong *ret_value,
> target_ulong new_value,
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c52c87faae..6f1f69eba6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -830,13 +830,15 @@ static RISCVException seed(CPURISCVState *env, int csrno)
> }
>
> /* zicfiss CSR_SSP read and write */
> -static int read_ssp(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_ssp(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = env->ssp;
> return RISCV_EXCP_NONE;
> }
>
> -static int write_ssp(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_ssp(CPURISCVState *env, int csrno,
> + target_ulong val, uintptr_t ra)
I like the RISCVException type correction.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2025-04-25 22:40 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-25 15:23 [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 15:23 ` [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn Richard Henderson
2025-04-25 22:28 ` Philippe Mathieu-Daudé [this message]
2025-04-28 22:33 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64 Richard Henderson
2025-04-25 22:29 ` Philippe Mathieu-Daudé
2025-04-28 22:34 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128 Richard Henderson
2025-04-25 22:29 ` Philippe Mathieu-Daudé
2025-04-28 22:34 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw Richard Henderson
2025-04-25 22:31 ` Philippe Mathieu-Daudé
2025-04-28 22:36 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128 Richard Henderson
2025-04-25 22:32 ` Philippe Mathieu-Daudé
2025-04-28 22:37 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 6/7] target/riscv: Move insn_len to internals.h Richard Henderson
2025-04-25 22:33 ` Philippe Mathieu-Daudé
2025-04-28 22:37 ` Alistair Francis
2025-04-25 15:23 ` [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 22:33 ` Philippe Mathieu-Daudé
2025-04-28 22:39 ` Alistair Francis
2025-04-29 14:33 ` Richard Henderson
2025-04-30 22:44 ` Alistair Francis
2025-05-14 21:33 ` Daniel Henrique Barboza
2025-05-15 8:10 ` Richard Henderson
2025-04-26 8:25 ` [PATCH 0/7] " Daniel Henrique Barboza
2025-04-28 22:46 ` Alistair Francis
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