From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgYqX-0001ZA-Ej for qemu-devel@nongnu.org; Mon, 28 Sep 2015 09:52:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZgYqT-0002nr-HZ for qemu-devel@nongnu.org; Mon, 28 Sep 2015 09:52:01 -0400 Received: from smtpbg299.qq.com ([184.105.67.99]:57818) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgYqT-0002lL-9W for qemu-devel@nongnu.org; Mon, 28 Sep 2015 09:51:57 -0400 Sender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com Date: Mon, 28 Sep 2015 21:51:27 +0800 Message-Id: <1443448287-4433-1-git-send-email-gang.chen.5i5j@gmail.com> Subject: [Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, rth@twiddle.net Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang From: Chen Gang At present, qemu x86_64 host backend can not remove the related dummy instructions. Even the worse, sometimes, it will generate the incorrect instructions which will cause segment fault for prefetch_l3 instruction. Signed-off-by: Chen Gang --- target-tilegx/translate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 86da6b5..7232361 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, memop = MO_TEQ; mnemonic = "ld"; do_load: - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); + if (dest != TILEGX_R_ZERO) { + tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); + } break; case OE_RR_X1(LDNA): tcg_gen_andi_tl(tdest, tsrca, ~7); @@ -1987,8 +1989,10 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) memop = MO_TEQ; mnemonic = "ld"; do_load: - tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), - dc->mmuidx, memop); + if (srcbdest != TILEGX_R_ZERO) { + tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), + dc->mmuidx, memop); + } qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, reg_names[srcbdest], reg_names[srca]); return TILEGX_EXCP_NONE; -- 1.9.3