* [Qemu-devel] [PATCH 01/14] target-tilegx: Use V1 in simd_helper.c
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 02/14] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions Richard Henderson
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
This will tidy up lots of cases where we'll want
to replicate a byte across the 8 elements of the word.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/simd_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index b931929..774def4 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -23,12 +23,16 @@
#include "exec/helper-proto.h"
+/* Broadcast a value to all elements of a vector. */
+#define V1(X) (((X) & 0xff) * 0x0101010101010101ull)
+
+
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
uint64_t m;
b &= 7;
- m = 0x0101010101010101ULL * (0xff >> b);
+ m = V1(0xff >> b);
return (a & m) << b;
}
@@ -37,7 +41,7 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b)
uint64_t m;
b &= 7;
- m = 0x0101010101010101ULL * ((0xff << b) & 0xff);
+ m = V1(0xff << b);
return (a & m) >> b;
}
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 02/14] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 01/14] target-tilegx: Use V1 in simd_helper.c Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 03/14] target-tilegx: Implement v*add and v*sub instructions Richard Henderson
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
v2sh* are implemented with helper functions; v4sh* are implmeneted
with inline code.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.h | 3 +++
target-tilegx/simd_helper.c | 32 ++++++++++++++++++++++++++++++++
target-tilegx/translate.c | 39 +++++++++++++++++++++++++++++++++++++++
3 files changed, 74 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 766f5f2..b253722 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -8,3 +8,6 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 774def4..f815731 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -25,6 +25,7 @@
/* Broadcast a value to all elements of a vector. */
#define V1(X) (((X) & 0xff) * 0x0101010101010101ull)
+#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
uint64_t helper_v1shl(uint64_t a, uint64_t b)
@@ -36,6 +37,15 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b)
return (a & m) << b;
}
+uint64_t helper_v2shl(uint64_t a, uint64_t b)
+{
+ uint64_t m;
+
+ b &= 15;
+ m = V2(0xffff >> b);
+ return (a & m) << b;
+}
+
uint64_t helper_v1shru(uint64_t a, uint64_t b)
{
uint64_t m;
@@ -45,6 +55,15 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b)
return (a & m) >> b;
}
+uint64_t helper_v2shru(uint64_t a, uint64_t b)
+{
+ uint64_t m;
+
+ b &= 15;
+ m = V2(0xffff << b);
+ return (a & m) >> b;
+}
+
uint64_t helper_v1shrs(uint64_t a, uint64_t b)
{
uint64_t r = 0;
@@ -57,3 +76,16 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b)
}
return r;
}
+
+uint64_t helper_v2shrs(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ b &= 15;
+ for (i = 0; i < 64; i += 16) {
+ int64_t ae = (int16_t)(a >> i);
+ r |= ((ae >> b) & 0xffff) << i;
+ }
+ return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e70c3e5..9228751 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -339,6 +339,25 @@ static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb
return TILEGX_EXCP_NONE;
}
+static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
+ void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 al = tcg_temp_new_i32();
+ TCGv_i32 ah = tcg_temp_new_i32();
+ TCGv_i32 bl = tcg_temp_new_i32();
+
+ tcg_gen_extr_i64_i32(al, ah, a64);
+ tcg_gen_extrl_i64_i32(bl, b64);
+ tcg_gen_andi_i32(bl, bl, 31);
+ generate(al, al, bl);
+ generate(ah, ah, bl);
+ tcg_gen_concat_i32_i64(d64, al, ah);
+
+ tcg_temp_free_i32(al);
+ tcg_temp_free_i32(ah);
+ tcg_temp_free_i32(bl);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -1144,12 +1163,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V2SADU, 0, X0):
case OE_RRR(V2SHLSC, 0, X0):
case OE_RRR(V2SHLSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2SHL, 0, X0):
case OE_RRR(V2SHL, 0, X1):
+ gen_helper_v2shl(tdest, tsrca, tsrcb);
+ mnemonic = "v2shl";
+ break;
case OE_RRR(V2SHRS, 0, X0):
case OE_RRR(V2SHRS, 0, X1):
+ gen_helper_v2shrs(tdest, tsrca, tsrcb);
+ mnemonic = "v2shrs";
+ break;
case OE_RRR(V2SHRU, 0, X0):
case OE_RRR(V2SHRU, 0, X1):
+ gen_helper_v2shru(tdest, tsrca, tsrcb);
+ mnemonic = "v2shru";
+ break;
case OE_RRR(V2SUBSC, 0, X0):
case OE_RRR(V2SUBSC, 0, X1):
case OE_RRR(V2SUB, 0, X0):
@@ -1174,12 +1203,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V4PACKSC, 0, X1):
case OE_RRR(V4SHLSC, 0, X0):
case OE_RRR(V4SHLSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4SHL, 0, X0):
case OE_RRR(V4SHL, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
+ mnemonic = "v4shl";
+ break;
case OE_RRR(V4SHRS, 0, X0):
case OE_RRR(V4SHRS, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
+ mnemonic = "v4shrs";
+ break;
case OE_RRR(V4SHRU, 0, X0):
case OE_RRR(V4SHRU, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
+ mnemonic = "v4shru";
+ break;
case OE_RRR(V4SUBSC, 0, X0):
case OE_RRR(V4SUBSC, 0, X1):
case OE_RRR(V4SUB, 0, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 03/14] target-tilegx: Implement v*add and v*sub instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 01/14] target-tilegx: Use V1 in simd_helper.c Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 02/14] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 04/14] target-tilegx: Implement v1multu instruction Richard Henderson
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
[rth: Implement everything inline; handle v1addi and v2addi as well.]
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1442873918-3394-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 137 +++++++++++++++++++++++++++++++++++++++-------
1 file changed, 116 insertions(+), 21 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 9228751..14ebd07 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -96,6 +96,7 @@ typedef struct {
#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
#define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
+#define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull)
static void gen_exception(DisasContext *dc, TileExcp num)
@@ -275,6 +276,35 @@ static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
tcg_temp_free(t);
}
+static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TCGMemOp memop, const char *name)
+{
+ if (dest) {
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
+ dc->mmuidx, memop);
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
+ reg_names[srca], reg_names[srcb]);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
+ int imm, TCGMemOp memop, const char *name)
+{
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcb = load_gr(dc, srcb);
+
+ tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
+ tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
+ reg_names[srca], reg_names[srcb], imm);
+ return TILEGX_EXCP_NONE;
+}
+
/* Equality comparison with zero can be done quickly and efficiently. */
static void gen_v1cmpeq0(TCGv v)
{
@@ -310,33 +340,45 @@ static void gen_v1cmpne0(TCGv v)
tcg_temp_free(c);
}
-static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
- unsigned srcb, TCGMemOp memop, const char *name)
+/* Vector addition can be performed via arithmetic plus masking. It is
+ efficient this way only for 4 or more elements. */
+static void gen_v12add(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
{
- if (dest) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
- }
+ TCGv tmask = tcg_const_tl(~sign);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
- tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
- dc->mmuidx, memop);
+ /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */
+ tcg_gen_and_tl(t0, tsrca, tmask);
+ tcg_gen_and_tl(t1, tsrcb, tmask);
+ tcg_gen_add_tl(tdest, t0, t1);
+ tcg_gen_xor_tl(t0, tsrca, tsrcb);
+ tcg_gen_andc_tl(t0, t0, tmask);
+ tcg_gen_xor_tl(tdest, tdest, t0);
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
- reg_names[srca], reg_names[srcb]);
- return TILEGX_EXCP_NONE;
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(tmask);
}
-static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
- int imm, TCGMemOp memop, const char *name)
+/* Similarly for vector subtraction. */
+static void gen_v12sub(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
{
- TCGv tsrca = load_gr(dc, srca);
- TCGv tsrcb = load_gr(dc, srcb);
+ TCGv tsign = tcg_const_tl(sign);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
- tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
- tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+ /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */
+ tcg_gen_or_tl(t0, tsrca, tsign);
+ tcg_gen_andc_tl(t1, tsrcb, tsign);
+ tcg_gen_sub_tl(tdest, t0, t1);
+ tcg_gen_eqv_tl(t0, tsrca, tsrcb);
+ tcg_gen_and_tl(t0, t0, tsign);
+ tcg_gen_xor_tl(tdest, tdest, t0);
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
- reg_names[srca], reg_names[srcb], imm);
- return TILEGX_EXCP_NONE;
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(tsign);
}
static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
@@ -358,6 +400,26 @@ static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
tcg_temp_free_i32(bl);
}
+static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
+ void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 al = tcg_temp_new_i32();
+ TCGv_i32 ah = tcg_temp_new_i32();
+ TCGv_i32 bl = tcg_temp_new_i32();
+ TCGv_i32 bh = tcg_temp_new_i32();
+
+ tcg_gen_extr_i64_i32(al, ah, a64);
+ tcg_gen_extr_i64_i32(bl, bh, b64);
+ generate(al, al, bl);
+ generate(ah, ah, bh);
+ tcg_gen_concat_i32_i64(d64, al, ah);
+
+ tcg_temp_free_i32(al);
+ tcg_temp_free_i32(ah);
+ tcg_temp_free_i32(bl);
+ tcg_temp_free_i32(bh);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -1043,8 +1105,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(V1ADDUC, 0, X0):
case OE_RRR(V1ADDUC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1ADD, 0, X0):
case OE_RRR(V1ADD, 0, X1):
+ gen_v12add(tdest, tsrca, tsrcb, V1_IMM(0x80));
+ mnemonic = "v1add";
+ break;
case OE_RRR(V1ADIFFU, 0, X0):
case OE_RRR(V1AVGU, 0, X0):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
@@ -1114,12 +1180,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(V1SUBUC, 0, X0):
case OE_RRR(V1SUBUC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1SUB, 0, X0):
case OE_RRR(V1SUB, 0, X1):
+ gen_v12sub(tdest, tsrca, tsrcb, V1_IMM(0x80));
+ mnemonic = "v1sub";
+ break;
case OE_RRR(V2ADDSC, 0, X0):
case OE_RRR(V2ADDSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2ADD, 0, X0):
case OE_RRR(V2ADD, 0, X1):
+ gen_v12add(tdest, tsrca, tsrcb, V2_IMM(0x8000));
+ mnemonic = "v2add";
+ break;
case OE_RRR(V2ADIFFS, 0, X0):
case OE_RRR(V2AVGS, 0, X0):
case OE_RRR(V2CMPEQ, 0, X0):
@@ -1181,13 +1255,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(V2SUBSC, 0, X0):
case OE_RRR(V2SUBSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2SUB, 0, X0):
case OE_RRR(V2SUB, 0, X1):
+ gen_v12sub(tdest, tsrca, tsrcb, V2_IMM(0x8000));
+ mnemonic = "v2sub";
+ break;
case OE_RRR(V4ADDSC, 0, X0):
case OE_RRR(V4ADDSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4ADD, 0, X0):
case OE_RRR(V4ADD, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
+ mnemonic = "v4add";
+ break;
case OE_RRR(V4INT_H, 0, X0):
case OE_RRR(V4INT_H, 0, X1):
tcg_gen_shri_tl(tdest, tsrcb, 32);
@@ -1221,9 +1302,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(V4SUBSC, 0, X0):
case OE_RRR(V4SUBSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4SUB, 0, X0):
case OE_RRR(V4SUB, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_v4op(tdest, tsrca, tsrcb, tcg_gen_sub_i32);
+ mnemonic = "v2sub";
+ break;
case OE_RRR(XOR, 0, X0):
case OE_RRR(XOR, 0, X1):
case OE_RRR(XOR, 5, Y0):
@@ -1364,6 +1448,11 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
break;
case OE_IM(V1ADDI, X0):
case OE_IM(V1ADDI, X1):
+ t0 = tcg_const_tl(V1_IMM(imm));
+ gen_v12add(tdest, tsrca, t0, V1_IMM(0x80));
+ tcg_temp_free(t0);
+ mnemonic = "v1addi";
+ break;
case OE_IM(V1CMPEQI, X0):
case OE_IM(V1CMPEQI, X1):
tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm));
@@ -1378,8 +1467,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(V1MAXUI, X1):
case OE_IM(V1MINUI, X0):
case OE_IM(V1MINUI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(V2ADDI, X0):
case OE_IM(V2ADDI, X1):
+ t0 = tcg_const_tl(V2_IMM(imm));
+ gen_v12add(tdest, tsrca, t0, V2_IMM(0x8000));
+ tcg_temp_free(t0);
+ mnemonic = "v2addi";
+ break;
case OE_IM(V2CMPEQI, X0):
case OE_IM(V2CMPEQI, X1):
case OE_IM(V2CMPLTSI, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 04/14] target-tilegx: Implement v1multu instruction
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (2 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 03/14] target-tilegx: Implement v*add and v*sub instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 05/14] target-tilegx: Implement crc instructions Richard Henderson
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.h | 1 +
target-tilegx/simd_helper.c | 13 +++++++++++++
target-tilegx/translate.c | 4 ++++
3 files changed, 18 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index b253722..d380d3b 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -5,6 +5,7 @@ DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index f815731..23c20bd 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -28,6 +28,19 @@
#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
+uint64_t helper_v1multu(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ uint64_t ae = (uint8_t)(a >> i);
+ uint64_t be = (uint8_t)(b >> i);
+ r |= ((ae * be) & 0xff) << i;
+ }
+ return r;
+}
+
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
uint64_t m;
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 14ebd07..6bfb1af 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1155,7 +1155,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V1MINU, 0, X1):
case OE_RRR(V1MNZ, 0, X0):
case OE_RRR(V1MNZ, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1MULTU, 0, X0):
+ gen_helper_v1multu(tdest, tsrca, tsrcb);
+ mnemonic = "v1multu";
+ break;
case OE_RRR(V1MULUS, 0, X0):
case OE_RRR(V1MULU, 0, X0):
case OE_RRR(V1MZ, 0, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 05/14] target-tilegx: Implement crc instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (3 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 04/14] target-tilegx: Implement v1multu instruction Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 06/14] target-tilegx: Implement table index instructions Richard Henderson
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.c | 19 +++++++++++++++++++
target-tilegx/helper.h | 2 ++
target-tilegx/translate.c | 8 +++++++-
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index a01bb8d..cad5dae 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "exec/helper-proto.h"
+#include <zlib.h> /* For crc32 */
void helper_exception(CPUTLGState *env, uint32_t excp)
{
@@ -78,3 +79,21 @@ uint64_t helper_shufflebytes(uint64_t dest, uint64_t srca, uint64_t srcb)
return vdst;
}
+
+uint64_t helper_crc32_8(uint64_t accum, uint64_t input)
+{
+ uint8_t buf = input;
+
+ /* zlib crc32 converts the accumulator and output to one's complement. */
+ return crc32(accum ^ 0xffffffff, &buf, 1) ^ 0xffffffff;
+}
+
+uint64_t helper_crc32_32(uint64_t accum, uint64_t input)
+{
+ uint8_t buf[4];
+
+ stl_le_p(buf, input);
+
+ /* zlib crc32 converts the accumulator and output to one's complement. */
+ return crc32(accum ^ 0xffffffff, buf, 4) ^ 0xffffffff;
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index d380d3b..72c8e92 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -4,6 +4,8 @@ DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(crc32_8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(crc32_32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 6bfb1af..3e5a8ea 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -750,9 +750,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(CMULHR, 0, X0):
case OE_RRR(CMULH, 0, X0):
case OE_RRR(CMUL, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(CRC32_32, 0, X0):
+ gen_helper_crc32_32(tdest, tsrca, tsrcb);
+ mnemonic = "crc32_32";
+ break;
case OE_RRR(CRC32_8, 0, X0):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_crc32_8(tdest, tsrca, tsrcb);
+ mnemonic = "crc32_8";
+ break;
case OE_RRR(DBLALIGN2, 0, X0):
case OE_RRR(DBLALIGN2, 0, X1):
gen_dblaligni(tdest, tsrca, tsrcb, 16);
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 06/14] target-tilegx: Implement table index instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (4 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 05/14] target-tilegx: Implement crc instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 07/14] target-tilegx: Implement complex multiply instructions Richard Henderson
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 3e5a8ea..9f86fd3 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -627,12 +627,27 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RR_X0(TBLIDXB0):
case OE_RR_Y0(TBLIDXB0):
+ tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8);
+ mnemonic = "tblidxb0";
+ break;
case OE_RR_X0(TBLIDXB1):
case OE_RR_Y0(TBLIDXB1):
+ tcg_gen_shri_tl(tdest, tsrca, 8);
+ tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+ mnemonic = "tblidxb1";
+ break;
case OE_RR_X0(TBLIDXB2):
case OE_RR_Y0(TBLIDXB2):
+ tcg_gen_shri_tl(tdest, tsrca, 16);
+ tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+ mnemonic = "tblidxb2";
+ break;
case OE_RR_X0(TBLIDXB3):
case OE_RR_Y0(TBLIDXB3):
+ tcg_gen_shri_tl(tdest, tsrca, 24);
+ tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+ mnemonic = "tblidxb3";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 07/14] target-tilegx: Implement complex multiply instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (5 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 06/14] target-tilegx: Implement table index instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 08/14] target-tilegx: Let x1 pipe process bpt instruction only Richard Henderson
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.c | 40 ++++++++++++++++++++++++++++++++++++++++
target-tilegx/helper.h | 3 +++
target-tilegx/translate.c | 31 ++++++++++++++++++++++++++++++-
3 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index cad5dae..36b287f 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -97,3 +97,43 @@ uint64_t helper_crc32_32(uint64_t accum, uint64_t input)
/* zlib crc32 converts the accumulator and output to one's complement. */
return crc32(accum ^ 0xffffffff, buf, 4) ^ 0xffffffff;
}
+
+uint64_t helper_cmula(uint64_t srcd, uint64_t srca, uint64_t srcb)
+{
+ uint32_t reala = (int16_t)srca;
+ uint32_t imaga = (int16_t)(srca >> 16);
+ uint32_t realb = (int16_t)srcb;
+ uint32_t imagb = (int16_t)(srcb >> 16);
+ uint32_t reald = srcd;
+ uint32_t imagd = srcd >> 32;
+ uint32_t realr = reala * realb - imaga * imagb + reald;
+ uint32_t imagr = reala * imagb + imaga * realb + imagd;
+
+ return deposit64(realr, 32, 32, imagr);
+}
+
+uint64_t helper_cmulaf(uint64_t srcd, uint64_t srca, uint64_t srcb)
+{
+ uint32_t reala = (int16_t)srca;
+ uint32_t imaga = (int16_t)(srca >> 16);
+ uint32_t realb = (int16_t)srcb;
+ uint32_t imagb = (int16_t)(srcb >> 16);
+ uint32_t reald = (int16_t)srcd;
+ uint32_t imagd = (int16_t)(srcd >> 16);
+ int32_t realr = reala * realb - imaga * imagb;
+ int32_t imagr = reala * imagb + imaga * realb;
+
+ return deposit32((realr >> 15) + reald, 16, 16, (imagr >> 15) + imagd);
+}
+
+uint64_t helper_cmul2(uint64_t srca, uint64_t srcb, int shift, int round)
+{
+ uint32_t reala = (int16_t)srca;
+ uint32_t imaga = (int16_t)(srca >> 16);
+ uint32_t realb = (int16_t)srcb;
+ uint32_t imagb = (int16_t)(srcb >> 16);
+ int32_t realr = reala * realb - imaga * imagb + round;
+ int32_t imagr = reala * imagb + imaga * realb + round;
+
+ return deposit32(realr >> shift, 16, 16, imagr >> shift);
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 72c8e92..82d84f1 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -6,6 +6,9 @@ DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(crc32_8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(crc32_32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int)
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 9f86fd3..d7e4d52 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -276,6 +276,15 @@ static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
tcg_temp_free(t);
}
+static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)
+{
+ TCGv_i32 tsh = tcg_const_i32(sh);
+ TCGv_i32 trd = tcg_const_i32(rd);
+ gen_helper_cmul2(tdest, tsrca, tsrcb, tsh, trd);
+ tcg_temp_free_i32(tsh);
+ tcg_temp_free_i32(trd);
+}
+
static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
unsigned srcb, TCGMemOp memop, const char *name)
{
@@ -759,13 +768,33 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
mnemonic = "cmpne";
break;
case OE_RRR(CMULAF, 0, X0):
+ gen_helper_cmulaf(tdest, load_gr(dc, dest), tsrca, tsrcb);
+ mnemonic = "cmulaf";
+ break;
case OE_RRR(CMULA, 0, X0):
+ gen_helper_cmula(tdest, load_gr(dc, dest), tsrca, tsrcb);
+ mnemonic = "cmula";
+ break;
case OE_RRR(CMULFR, 0, X0):
+ gen_cmul2(tdest, tsrca, tsrcb, 15, 1 << 14);
+ mnemonic = "cmulfr";
+ break;
case OE_RRR(CMULF, 0, X0):
+ gen_cmul2(tdest, tsrca, tsrcb, 15, 0);
+ mnemonic = "cmulf";
+ break;
case OE_RRR(CMULHR, 0, X0):
+ gen_cmul2(tdest, tsrca, tsrcb, 16, 1 << 15);
+ mnemonic = "cmulhr";
+ break;
case OE_RRR(CMULH, 0, X0):
+ gen_cmul2(tdest, tsrca, tsrcb, 16, 0);
+ mnemonic = "cmulh";
+ break;
case OE_RRR(CMUL, 0, X0):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_cmula(tdest, load_zero(dc), tsrca, tsrcb);
+ mnemonic = "cmul";
+ break;
case OE_RRR(CRC32_32, 0, X0):
gen_helper_crc32_32(tdest, tsrca, tsrcb);
mnemonic = "crc32_32";
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 08/14] target-tilegx: Let x1 pipe process bpt instruction only
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (6 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 07/14] target-tilegx: Implement complex multiply instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 09/14] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel Richard Henderson
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
According to the related document, bpt can be only in x1 pipe.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index d7e4d52..3566b88 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -458,8 +458,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
mnemonic = "flushwb";
goto done0;
case OE_RR_X1(ILL):
+ if (dest == 0x1c && srca == 0x25) {
+ mnemonic = "bpt";
+ goto done2;
+ }
+ /* Fall through */
case OE_RR_Y1(ILL):
- mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
+ mnemonic = "ill";
+ done2:
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
return TILEGX_EXCP_OPCODE_UNKNOWN;
case OE_RR_X1(MF):
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 09/14] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (7 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 08/14] target-tilegx: Let x1 pipe process bpt instruction only Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 10/14] linux-user/tilegx: Implement tilegx signal features Richard Henderson
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
They content several new macro members, also contents TARGET_N*.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443240605-2924-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/syscall_defs.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index cdc8db4..fd2b5eb 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -744,6 +744,10 @@ typedef struct target_siginfo {
#define TARGET_ILL_PRVREG (6) /* privileged register */
#define TARGET_ILL_COPROC (7) /* coprocessor error */
#define TARGET_ILL_BADSTK (8) /* internal stack error */
+#ifdef TARGET_TILEGX
+#define TARGET_ILL_DBLFLT (9) /* double fault */
+#define TARGET_ILL_HARDWALL (10) /* user networks hardwall violation */
+#endif
/*
* SIGFPE si_codes
@@ -763,6 +767,7 @@ typedef struct target_siginfo {
*/
#define TARGET_SEGV_MAPERR (1) /* address not mapped to object */
#define TARGET_SEGV_ACCERR (2) /* invalid permissions for mapped object */
+#define TARGET_SEGV_BNDERR (3) /* failed address bound checks */
/*
* SIGBUS si_codes
@@ -770,12 +775,18 @@ typedef struct target_siginfo {
#define TARGET_BUS_ADRALN (1) /* invalid address alignment */
#define TARGET_BUS_ADRERR (2) /* non-existent physical address */
#define TARGET_BUS_OBJERR (3) /* object specific hardware error */
+/* hardware memory error consumed on a machine check: action required */
+#define TARGET_BUS_MCEERR_AR (4)
+/* hardware memory error detected in process but not consumed: action optional*/
+#define TARGET_BUS_MCEERR_AO (5)
/*
* SIGTRAP si_codes
*/
#define TARGET_TRAP_BRKPT (1) /* process breakpoint */
#define TARGET_TRAP_TRACE (2) /* process trace trap */
+#define TARGET_TRAP_BRANCH (3) /* process taken branch trap */
+#define TARGET_TRAP_HWBKPT (4) /* hardware breakpoint/watchpoint */
#endif /* defined(TARGET_I386) || defined(TARGET_ARM) */
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 10/14] linux-user/tilegx: Implement tilegx signal features
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (8 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 09/14] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 11/14] target-tilegx: Decode ill pseudo-instructions Richard Henderson
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
[rth: Remove the spreg[EX1] handling, as it's irrelevant to user-mode.]
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443312618-13641-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/signal.c | 160 +++++++++++++++++++++++++++++++++++++++++++-
linux-user/tilegx/syscall.h | 3 +
2 files changed, 162 insertions(+), 1 deletion(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 502efd9..a84e9cd 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -5543,6 +5543,163 @@ long do_rt_sigreturn(CPUAlphaState *env)
force_sig(TARGET_SIGSEGV);
}
+#elif defined(TARGET_TILEGX)
+
+struct target_sigcontext {
+ union {
+ /* General-purpose registers. */
+ abi_ulong gregs[56];
+ struct {
+ abi_ulong __gregs[53];
+ abi_ulong tp; /* Aliases gregs[TREG_TP]. */
+ abi_ulong sp; /* Aliases gregs[TREG_SP]. */
+ abi_ulong lr; /* Aliases gregs[TREG_LR]. */
+ };
+ };
+ abi_ulong pc; /* Program counter. */
+ abi_ulong ics; /* In Interrupt Critical Section? */
+ abi_ulong faultnum; /* Fault number. */
+ abi_ulong pad[5];
+};
+
+struct target_ucontext {
+ abi_ulong tuc_flags;
+ abi_ulong tuc_link;
+ target_stack_t tuc_stack;
+ struct target_sigcontext tuc_mcontext;
+ target_sigset_t tuc_sigmask; /* mask last for extensibility */
+};
+
+struct target_rt_sigframe {
+ unsigned char save_area[16]; /* caller save area */
+ struct target_siginfo info;
+ struct target_ucontext uc;
+};
+
+static void setup_sigcontext(struct target_sigcontext *sc,
+ CPUArchState *env, int signo)
+{
+ int i;
+
+ for (i = 0; i < TILEGX_R_COUNT; ++i) {
+ __put_user(env->regs[i], &sc->gregs[i]);
+ }
+
+ __put_user(env->pc, &sc->pc);
+ __put_user(0, &sc->ics);
+ __put_user(signo, &sc->faultnum);
+}
+
+static void restore_sigcontext(CPUTLGState *env, struct target_sigcontext *sc)
+{
+ int i;
+
+ for (i = 0; i < TILEGX_R_COUNT; ++i) {
+ __get_user(env->regs[i], &sc->gregs[i]);
+ }
+
+ __get_user(env->pc, &sc->pc);
+}
+
+static abi_ulong get_sigframe(struct target_sigaction *ka, CPUArchState *env,
+ size_t frame_size)
+{
+ unsigned long sp = env->regs[TILEGX_R_SP];
+
+ if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size))) {
+ return -1UL;
+ }
+
+ if ((ka->sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) {
+ sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size;
+ }
+
+ sp -= frame_size;
+ sp &= -16UL;
+ return sp;
+}
+
+static void setup_rt_frame(int sig, struct target_sigaction *ka,
+ target_siginfo_t *info,
+ target_sigset_t *set, CPUArchState *env)
+{
+ abi_ulong frame_addr;
+ struct target_rt_sigframe *frame;
+ unsigned long restorer;
+
+ frame_addr = get_sigframe(ka, env, sizeof(*frame));
+ if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
+ goto give_sigsegv;
+ }
+
+ /* Always write at least the signal number for the stack backtracer. */
+ if (ka->sa_flags & TARGET_SA_SIGINFO) {
+ /* At sigreturn time, restore the callee-save registers too. */
+ tswap_siginfo(&frame->info, info);
+ /* regs->flags |= PT_FLAGS_RESTORE_REGS; FIXME: we can skip it? */
+ } else {
+ __put_user(info->si_signo, &frame->info.si_signo);
+ }
+
+ /* Create the ucontext. */
+ __put_user(0, &frame->uc.tuc_flags);
+ __put_user(0, &frame->uc.tuc_link);
+ __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp);
+ __put_user(sas_ss_flags(env->regs[TILEGX_R_SP]),
+ &frame->uc.tuc_stack.ss_flags);
+ __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size);
+ setup_sigcontext(&frame->uc.tuc_mcontext, env, info->si_signo);
+
+ restorer = (unsigned long) do_rt_sigreturn;
+ if (ka->sa_flags & TARGET_SA_RESTORER) {
+ restorer = (unsigned long) ka->sa_restorer;
+ }
+ env->pc = (unsigned long) ka->_sa_handler;
+ env->regs[TILEGX_R_SP] = (unsigned long) frame;
+ env->regs[TILEGX_R_LR] = restorer;
+ env->regs[0] = (unsigned long) sig;
+ env->regs[1] = (unsigned long) &frame->info;
+ env->regs[2] = (unsigned long) &frame->uc;
+ /* regs->flags |= PT_FLAGS_CALLER_SAVES; FIXME: we can skip it? */
+
+ unlock_user_struct(frame, frame_addr, 1);
+ return;
+
+give_sigsegv:
+ if (sig == TARGET_SIGSEGV) {
+ ka->_sa_handler = TARGET_SIG_DFL;
+ }
+ force_sig(TARGET_SIGSEGV /* , current */);
+}
+
+long do_rt_sigreturn(CPUTLGState *env)
+{
+ abi_ulong frame_addr = env->regs[TILEGX_R_SP];
+ struct target_rt_sigframe *frame;
+ sigset_t set;
+
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
+ goto badframe;
+ }
+ target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
+ do_sigprocmask(SIG_SETMASK, &set, NULL);
+
+ restore_sigcontext(env, &frame->uc.tuc_mcontext);
+ if (do_sigaltstack(frame_addr + offsetof(struct target_rt_sigframe,
+ uc.tuc_stack),
+ 0, env->regs[TILEGX_R_SP]) == -EFAULT) {
+ goto badframe;
+ }
+
+ unlock_user_struct(frame, frame_addr, 0);
+ return env->regs[TILEGX_R_RE];
+
+
+ badframe:
+ unlock_user_struct(frame, frame_addr, 0);
+ force_sig(TARGET_SIGSEGV);
+}
+
#else
static void setup_frame(int sig, struct target_sigaction *ka,
@@ -5662,7 +5819,8 @@ void process_pending_signals(CPUArchState *cpu_env)
}
#endif
/* prepare the stack frame of the virtual CPU */
-#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) \
+ || defined(TARGET_TILEGX)
/* These targets do not have traditional signals. */
setup_rt_frame(sig, sa, &q->info, &target_old_set, cpu_env);
#else
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
index 653ece1..a938d4e 100644
--- a/linux-user/tilegx/syscall.h
+++ b/linux-user/tilegx/syscall.h
@@ -37,4 +37,7 @@ struct target_pt_regs {
#define TARGET_MLOCKALL_MCL_CURRENT 1
#define TARGET_MLOCKALL_MCL_FUTURE 2
+/* For faultnum */
+#define TARGET_INT_SWINT_1 14
+
#endif
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 11/14] target-tilegx: Decode ill pseudo-instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (9 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 10/14] linux-user/tilegx: Implement tilegx signal features Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 12/14] target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV Richard Henderson
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
Notice raise and bpt, decoding the constants embedded in the
nop addil instruction in the x0 slot.
[rth: Generalize TILEGX_EXCP_OPCODE_ILL to TILEGX_EXCP_SIGNAL.
Drop validation of signal values.]
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443243635-4886-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/main.c | 14 ++++++++
target-tilegx/cpu.h | 5 ++-
target-tilegx/translate.c | 81 +++++++++++++++++++++++++++++++++++++++--------
3 files changed, 85 insertions(+), 15 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 25cf875..be3a7ad 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3436,6 +3436,17 @@ static void gen_sigill_reg(CPUTLGState *env)
queue_signal(env, info.si_signo, &info);
}
+static void do_signal(CPUTLGState *env)
+{
+ target_siginfo_t info;
+
+ info.si_signo = env->signo;
+ info.si_errno = 0;
+ info.si_code = env->sigcode;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, &info);
+}
+
static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
{
if (unlikely(reg >= TILEGX_R_COUNT)) {
@@ -3622,6 +3633,9 @@ void cpu_loop(CPUTLGState *env)
case TILEGX_EXCP_OPCODE_FETCHOR4:
do_fetch(env, trapnr, false);
break;
+ case TILEGX_EXCP_SIGNAL:
+ do_signal(env);
+ break;
case TILEGX_EXCP_REG_IDN_ACCESS:
case TILEGX_EXCP_REG_UDN_ACCESS:
gen_sigill_reg(env);
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index b9f5082..023ccd4 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -61,6 +61,7 @@ typedef enum {
TILEGX_EXCP_NONE = 0,
TILEGX_EXCP_SYSCALL = 1,
TILEGX_EXCP_SEGV = 2,
+ TILEGX_EXCP_SIGNAL = 3,
TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
@@ -87,10 +88,12 @@ typedef struct CPUTLGState {
uint64_t pc; /* Current pc */
#if defined(CONFIG_USER_ONLY)
+ uint64_t excaddr; /* exception address */
uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
uint64_t atomic_srcb;
uint32_t atomic_dstr;
- uint64_t excaddr; /* exception address */
+ uint32_t signo; /* Signal number */
+ uint32_t sigcode; /* Signal code */
#endif
CPU_COMMON
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 3566b88..54aa71d 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -23,6 +23,8 @@
#include "disas/disas.h"
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
+#include "linux-user/syscall_defs.h"
+
#include "opcode_tilegx.h"
#include "spr_def_64.h"
@@ -429,8 +431,66 @@ static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
tcg_temp_free_i32(bh);
}
+static TileExcp gen_signal(DisasContext *dc, int signo, int sigcode,
+ const char *mnemonic)
+{
+ TCGv_i32 t0 = tcg_const_i32(signo);
+ TCGv_i32 t1 = tcg_const_i32(sigcode);
+
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUTLGState, signo));
+ tcg_gen_st_i32(t1, cpu_env, offsetof(CPUTLGState, sigcode));
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
+ return TILEGX_EXCP_SIGNAL;
+}
+
+static bool parse_from_addli(uint64_t bundle, int *signo, int *sigcode)
+{
+ int imm;
+
+ if ((get_Opcode_X0(bundle) != ADDLI_OPCODE_X0)
+ || (get_Dest_X0(bundle) != TILEGX_R_ZERO)
+ || (get_SrcA_X0(bundle) != TILEGX_R_ZERO)) {
+ return false;
+ }
+
+ imm = get_Imm16_X0(bundle);
+ *signo = imm & 0x3f;
+ *sigcode = (imm >> 6) & 0xf;
+
+ /* ??? The linux kernel validates both signo and the sigcode vs the
+ known max for each signal. Don't bother here. */
+ return true;
+}
+
+static TileExcp gen_specill(DisasContext *dc, unsigned dest, unsigned srca,
+ uint64_t bundle)
+{
+ const char *mnemonic;
+ int signo;
+ int sigcode;
+
+ if (dest == 0x1c && srca == 0x25) {
+ signo = TARGET_SIGTRAP;
+ sigcode = TARGET_TRAP_BRKPT;
+ mnemonic = "bpt";
+ } else if (dest == 0x1d && srca == 0x25
+ && parse_from_addli(bundle, &signo, &sigcode)) {
+ mnemonic = "raise";
+ } else {
+ signo = TARGET_SIGILL;
+ sigcode = TARGET_ILL_ILLOPC;
+ mnemonic = "ill";
+ }
+
+ return gen_signal(dc, signo, sigcode, mnemonic);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
- unsigned dest, unsigned srca)
+ unsigned dest, unsigned srca, uint64_t bundle)
{
TCGv tdest, tsrca;
const char *mnemonic;
@@ -458,16 +518,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
mnemonic = "flushwb";
goto done0;
case OE_RR_X1(ILL):
- if (dest == 0x1c && srca == 0x25) {
- mnemonic = "bpt";
- goto done2;
- }
- /* Fall through */
+ return gen_specill(dc, dest, srca, bundle);
case OE_RR_Y1(ILL):
- mnemonic = "ill";
- done2:
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
- return TILEGX_EXCP_OPCODE_UNKNOWN;
+ return gen_signal(dc, TARGET_SIGILL, TARGET_ILL_ILLOPC, "ill");
case OE_RR_X1(MF):
mnemonic = "mf";
goto done0;
@@ -1909,7 +1962,7 @@ static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
case RRR_1_OPCODE_Y0:
if (ext == UNARY_RRR_1_OPCODE_Y0) {
ext = get_UnaryOpcodeExtension_Y0(bundle);
- return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
+ return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca, bundle);
}
/* fallthru */
case RRR_0_OPCODE_Y0:
@@ -1955,7 +2008,7 @@ static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
case RRR_1_OPCODE_Y1:
if (ext == UNARY_RRR_1_OPCODE_Y0) {
ext = get_UnaryOpcodeExtension_Y1(bundle);
- return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
+ return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca, bundle);
}
/* fallthru */
case RRR_0_OPCODE_Y1:
@@ -2057,7 +2110,7 @@ static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
ext = get_RRROpcodeExtension_X0(bundle);
if (ext == UNARY_RRR_0_OPCODE_X0) {
ext = get_UnaryOpcodeExtension_X0(bundle);
- return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
+ return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca, bundle);
}
srcb = get_SrcB_X0(bundle);
return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
@@ -2104,7 +2157,7 @@ static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
switch (ext) {
case UNARY_RRR_0_OPCODE_X1:
ext = get_UnaryOpcodeExtension_X1(bundle);
- return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
+ return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca, bundle);
case ST1_RRR_0_OPCODE_X1:
return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
case ST2_RRR_0_OPCODE_X1:
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 12/14] target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (10 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 11/14] target-tilegx: Decode ill pseudo-instructions Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 13/14] target-tilegx: Fix a typo for mnemonic about "ld_add" Richard Henderson
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
Consolidate signal handling under a single exception.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/main.c | 41 +++++++++++++++++++++++------------------
target-tilegx/cpu.c | 7 ++++++-
target-tilegx/cpu.h | 3 +--
3 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index be3a7ad..64daf87 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3414,17 +3414,6 @@ void cpu_loop(CPUS390XState *env)
#ifdef TARGET_TILEGX
-static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
-{
- target_siginfo_t info;
-
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = addr;
- queue_signal(env, info.si_signo, &info);
-}
-
static void gen_sigill_reg(CPUTLGState *env)
{
target_siginfo_t info;
@@ -3436,17 +3425,36 @@ static void gen_sigill_reg(CPUTLGState *env)
queue_signal(env, info.si_signo, &info);
}
-static void do_signal(CPUTLGState *env)
+static void do_signal(CPUTLGState *env, int signo, int sigcode)
{
target_siginfo_t info;
- info.si_signo = env->signo;
+ info.si_signo = signo;
info.si_errno = 0;
- info.si_code = env->sigcode;
info._sifields._sigfault._addr = env->pc;
+
+ if (signo == TARGET_SIGSEGV) {
+ /* The passed in sigcode is a dummy; check for a page mapping
+ and pass either MAPERR or ACCERR. */
+ target_ulong addr = env->excaddr;
+ info._sifields._sigfault._addr = addr;
+ if (page_check_range(addr, 1, PAGE_VALID) < 0) {
+ sigcode = TARGET_SEGV_MAPERR;
+ } else {
+ sigcode = TARGET_SEGV_ACCERR;
+ }
+ }
+ info.si_code = sigcode;
+
queue_signal(env, info.si_signo, &info);
}
+static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
+{
+ env->excaddr = addr;
+ do_signal(env, TARGET_SIGSEGV, 0);
+}
+
static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
{
if (unlikely(reg >= TILEGX_R_COUNT)) {
@@ -3634,15 +3642,12 @@ void cpu_loop(CPUTLGState *env)
do_fetch(env, trapnr, false);
break;
case TILEGX_EXCP_SIGNAL:
- do_signal(env);
+ do_signal(env, env->signo, env->sigcode);
break;
case TILEGX_EXCP_REG_IDN_ACCESS:
case TILEGX_EXCP_REG_UDN_ACCESS:
gen_sigill_reg(env);
break;
- case TILEGX_EXCP_SEGV:
- gen_sigsegv_maperr(env, env->excaddr);
- break;
default:
fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
g_assert_not_reached();
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
index 78b73e4..3c5481d 100644
--- a/target-tilegx/cpu.c
+++ b/target-tilegx/cpu.c
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
+#include "linux-user/syscall_defs.h"
static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
@@ -121,8 +122,12 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
{
TileGXCPU *cpu = TILEGX_CPU(cs);
- cs->exception_index = TILEGX_EXCP_SEGV;
+ /* The sigcode field will be filled in by do_signal in main.c. */
+ cs->exception_index = TILEGX_EXCP_SIGNAL;
cpu->env.excaddr = address;
+ cpu->env.signo = TARGET_SIGSEGV;
+ cpu->env.sigcode = 0;
+
return 1;
}
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 023ccd4..6f04fe7 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -60,8 +60,7 @@ enum {
typedef enum {
TILEGX_EXCP_NONE = 0,
TILEGX_EXCP_SYSCALL = 1,
- TILEGX_EXCP_SEGV = 2,
- TILEGX_EXCP_SIGNAL = 3,
+ TILEGX_EXCP_SIGNAL = 2,
TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 13/14] target-tilegx: Fix a typo for mnemonic about "ld_add"
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (11 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 12/14] target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
2015-10-01 2:38 ` [Qemu-devel] [PATCH 14/14] target-tilegx: Handle nofault prefetch instructions Richard Henderson
[not found] ` <560D3DC0.7010500@hotmail.com>
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
From: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443562720-3008-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 54aa71d..8fee60c 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1543,7 +1543,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
goto do_load_add;
case OE_IM(LD_ADD, X1):
memop = MO_TEQ;
- mnemonic = "ldnt_add";
+ mnemonic = "ld_add";
do_load_add:
tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 14/14] target-tilegx: Handle nofault prefetch instructions
2015-10-01 2:38 [Qemu-devel] [PATCH 00/14] Collected tilegx patches Richard Henderson
` (12 preceding siblings ...)
2015-10-01 2:38 ` [Qemu-devel] [PATCH 13/14] target-tilegx: Fix a typo for mnemonic about "ld_add" Richard Henderson
@ 2015-10-01 2:38 ` Richard Henderson
[not found] ` <560D3DC0.7010500@hotmail.com>
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2015-10-01 2:38 UTC (permalink / raw)
To: qemu-devel; +Cc: gang.chen.5i5j
These are mapped onto some of the normal load instructions, when the
destination is the zero register. Other load insns do fault even
when targeting the zero register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 40 ++++++++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 8fee60c..6ab66f9 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -496,6 +496,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
const char *mnemonic;
TCGMemOp memop;
TileExcp ret = TILEGX_EXCP_NONE;
+ bool prefetch_nofault = false;
/* Eliminate instructions with no output before doing anything else. */
switch (opext) {
@@ -609,27 +610,30 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
memop = MO_SB;
- mnemonic = "ld1s";
+ mnemonic = "ld1s"; /* prefetch_l1_fault */
goto do_load;
case OE_RR_X1(LD1U):
memop = MO_UB;
- mnemonic = "ld1u";
+ mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load;
case OE_RR_X1(LD2S):
memop = MO_TESW;
- mnemonic = "ld2s";
+ mnemonic = "ld2s"; /* prefetch_l2_fault */
goto do_load;
case OE_RR_X1(LD2U):
memop = MO_TEUW;
- mnemonic = "ld2u";
+ mnemonic = "ld2u"; /* prefetch_l2 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load;
case OE_RR_X1(LD4S):
memop = MO_TESL;
- mnemonic = "ld4s";
+ mnemonic = "ld4s"; /* prefetch_l3_fault */
goto do_load;
case OE_RR_X1(LD4U):
memop = MO_TEUL;
- mnemonic = "ld4u";
+ mnemonic = "ld4u"; /* prefetch_l3 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load;
case OE_RR_X1(LDNT1S):
memop = MO_SB;
@@ -663,7 +667,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ if (!prefetch_nofault) {
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ }
break;
case OE_RR_X1(LDNA):
tcg_gen_andi_tl(tdest, tsrca, ~7);
@@ -1442,6 +1448,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
{
TCGv tdest = dest_gr(dc, dest);
TCGv tsrca = load_gr(dc, srca);
+ bool prefetch_nofault = false;
const char *mnemonic;
TCGMemOp memop;
int i2, i3;
@@ -1491,27 +1498,30 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
break;
case OE_IM(LD1S_ADD, X1):
memop = MO_SB;
- mnemonic = "ld1s_add";
+ mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
goto do_load_add;
case OE_IM(LD1U_ADD, X1):
memop = MO_UB;
- mnemonic = "ld1u_add";
+ mnemonic = "ld1u_add"; /* prefetch_add_l1 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load_add;
case OE_IM(LD2S_ADD, X1):
memop = MO_TESW;
- mnemonic = "ld2s_add";
+ mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
goto do_load_add;
case OE_IM(LD2U_ADD, X1):
memop = MO_TEUW;
- mnemonic = "ld2u_add";
+ mnemonic = "ld2u_add"; /* prefetch_add_l2 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load_add;
case OE_IM(LD4S_ADD, X1):
memop = MO_TESL;
- mnemonic = "ld4s_add";
+ mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
goto do_load_add;
case OE_IM(LD4U_ADD, X1):
memop = MO_TEUL;
- mnemonic = "ld4u_add";
+ mnemonic = "ld4u_add"; /* prefetch_add_l3 */
+ prefetch_nofault = (dest == TILEGX_R_ZERO);
goto do_load_add;
case OE_IM(LDNT1S_ADD, X1):
memop = MO_SB;
@@ -1545,7 +1555,9 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
memop = MO_TEQ;
mnemonic = "ld_add";
do_load_add:
- tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ if (!prefetch_nofault) {
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ }
tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
break;
case OE_IM(LDNA_ADD, X1):
--
2.4.3
^ permalink raw reply related [flat|nested] 16+ messages in thread[parent not found: <560D3DC0.7010500@hotmail.com>]
* Re: [Qemu-devel] [PATCH 00/14] Collected tilegx patches
[not found] ` <560D3DC0.7010500@hotmail.com>
@ 2015-10-01 14:04 ` Chen Gang
0 siblings, 0 replies; 16+ messages in thread
From: Chen Gang @ 2015-10-01 14:04 UTC (permalink / raw)
To: rth@twiddle.net, qemu-devel
On 10/1/15 10:38, Richard Henderson wrote:
> I've taken the liberty of modifying some of the patches that Chen Gang
> has posted. Some of these are new cleanups that I saw along the way.
> A few are filling out the final user-level non-fp, non-vector insns.
>
Thank you very much for your work.
> Please give them a look over and re-test, Mr Chen.
>
OK, I shall try.
>
> Chen Gang (8):
> target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
> target-tilegx: Implement v*add and v*sub instructions
> target-tilegx: Implement v1multu instruction
> target-tilegx: Let x1 pipe process bpt instruction only
> linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel
> linux-user/tilegx: Implement tilegx signal features
> target-tilegx: Decode ill pseudo-instructions
> target-tilegx: Fix a typo for mnemonic about "ld_add"
>
> Richard Henderson (6):
> target-tilegx: Use V1 in simd_helper.c
> target-tilegx: Implement crc instructions
> target-tilegx: Implement table index instructions
> target-tilegx: Implement complex multiply instructions
> target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV
> target-tilegx: Handle nofault prefetch instructions
>
> linux-user/main.c | 39 +++--
> linux-user/signal.c | 160 +++++++++++++++++++-
> linux-user/syscall_defs.h | 11 ++
> linux-user/tilegx/syscall.h | 3 +
> target-tilegx/cpu.c | 7 +-
> target-tilegx/cpu.h | 6 +-
> target-tilegx/helper.c | 59 ++++++++
> target-tilegx/helper.h | 9 ++
> target-tilegx/simd_helper.c | 53 ++++++-
> target-tilegx/translate.c | 349 ++++++++++++++++++++++++++++++++++++++------
> 10 files changed, 635 insertions(+), 61 deletions(-)
>
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 16+ messages in thread