From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhd78-000436-Ey for qemu-devel@nongnu.org; Thu, 01 Oct 2015 08:37:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zhd74-0006JJ-A7 for qemu-devel@nongnu.org; Thu, 01 Oct 2015 08:37:34 -0400 Received: from smtpbg63.qq.com ([103.7.29.150]:14421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhd73-0006J1-MJ for qemu-devel@nongnu.org; Thu, 01 Oct 2015 08:37:30 -0400 Sender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com Date: Thu, 1 Oct 2015 20:37:15 +0800 Message-Id: <1443703035-4433-1-git-send-email-gang.chen.5i5j@gmail.com> Subject: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, rth@twiddle.net Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang From: Chen Gang Acording to the __longjmp tilegx libc implementation, and reference from tilegx ISA document, and suggested by tilegx architecture member, we can treat iret instruction as "jrp lr". The related code is below: ENTRY (__longjmp) FEEDBACK_ENTER(__longjmp) #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE } FOR_EACH_CALLEE_SAVED_REG(RESTORE) { LD r2, r0 ; retrieve ICS bit from jmp_buf movei r3, 1 CMPEQI r0, r1, 0 } { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori r2, r2, RETURN_PL } { or r0, r1, r0 mtspr EX_CONTEXT_0_1, r2 } iret jrp lr Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so just skip them, at present. "jrp lr" in __longjmp is for historical reasons, and might get removed in the future. After this patch, busybox sh can run correctly. Signed-off-by: Chen Gang --- target-tilegx/translate.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 421766b..b7bb4f3 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -563,8 +563,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, break; case OE_RR_X0(FSINGLE_PACK1): case OE_RR_Y0(FSINGLE_PACK1): - case OE_RR_X1(IRET): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + case OE_RR_X1(IRET): + if (srca) { + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + } + srca = TILEGX_R_LR; + mnemonic = "iret"; + goto do_jr; case OE_RR_X1(LD1S): memop = MO_SB; mnemonic = "ld1s"; /* prefetch_l1_fault */ @@ -1823,6 +1829,8 @@ static const TileSPR *find_spr(unsigned spr) offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0) D(SIM_CONTROL, offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0) + D(EX_CONTEXT_0_0, -1, 0, 0) /* Skip it */ + D(EX_CONTEXT_0_1, -1, 0, 0) /* Skip it */ } #undef D @@ -1836,9 +1844,11 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca) const TileSPR *def = find_spr(spr); TCGv tsrca; - if (def == NULL) { + if (!def) { qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]); return TILEGX_EXCP_OPCODE_UNKNOWN; + } else if (def->offset == -1) { + goto tail; } tsrca = load_gr(dc, srca); @@ -1847,6 +1857,8 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca) } else { tcg_gen_st_tl(tsrca, cpu_env, def->offset); } + +tail: qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]); return TILEGX_EXCP_NONE; } @@ -1856,7 +1868,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr) const TileSPR *def = find_spr(spr); TCGv tdest; - if (def == NULL) { + if (!def || def->offset == -1) { qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr); return TILEGX_EXCP_OPCODE_UNKNOWN; } -- 1.9.3