From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhoXZ-00043q-Gu for qemu-devel@nongnu.org; Thu, 01 Oct 2015 20:49:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhoXW-0000dW-3k for qemu-devel@nongnu.org; Thu, 01 Oct 2015 20:49:37 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:35077) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhoXV-0000dI-V0 for qemu-devel@nongnu.org; Thu, 01 Oct 2015 20:49:34 -0400 Received: by pacfv12 with SMTP id fv12so91934631pac.2 for ; Thu, 01 Oct 2015 17:49:33 -0700 (PDT) From: "Edgar E. Iglesias" Date: Thu, 1 Oct 2015 17:49:21 -0700 Message-Id: <1443746968-9389-2-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1443746968-9389-1-git-send-email-edgar.iglesias@gmail.com> References: <1443746968-9389-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 1/8] target-arm: Add HPFAR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 1 + target-arm/helper.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cc1578c..895f2c2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -278,6 +278,7 @@ typedef struct CPUARMState { }; uint64_t far_el[4]; }; + uint64_t hpfar_el2; union { /* Translation result. */ struct { uint64_t _unused_par_0; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8367997..5a5e5f0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, + .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0, .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, #endif + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, .accessfn = access_el3_aa32ns, + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, REGINFO_SENTINEL }; -- 1.9.1