From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com,
alex.bennee@linaro.org, agraf@suse.de
Subject: [Qemu-devel] [PATCH v2 4/8] target-arm: Avoid inline for get_phys_addr
Date: Thu, 1 Oct 2015 17:49:24 -0700 [thread overview]
Message-ID: <1443746968-9389-5-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1443746968-9389-1-git-send-email-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Avoid inline for get_phys_addr() to prepare for future recursive use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2701788..51b0e61 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -15,10 +15,10 @@
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#ifndef CONFIG_USER_ONLY
-static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
- int access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size, uint32_t *fsr);
+static bool get_phys_addr(CPUARMState *env, target_ulong address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
+ target_ulong *page_size, uint32_t *fsr);
/* Definitions for the PMCCNTR and PMCR registers */
#define PMCRD 0x8
@@ -6968,10 +6968,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
* @page_size: set to the size of the page containing phys_ptr
* @fsr: set to the DFSR/IFSR value on failure
*/
-static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
- int access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size, uint32_t *fsr)
+static bool get_phys_addr(CPUARMState *env, target_ulong address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
+ target_ulong *page_size, uint32_t *fsr)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
/* TODO: when we support EL2 we should here call ourselves recursively
--
1.9.1
next prev parent reply other threads:[~2015-10-02 0:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-02 0:49 [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 1/8] target-arm: Add HPFAR_EL2 Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 2/8] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 3/8] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-02 0:49 ` Edgar E. Iglesias [this message]
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 5/8] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-03 2:10 ` Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 6/8] target-arm: Add S2 translation support for S1 PTW Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 7/8] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-02 0:49 ` [Qemu-devel] [PATCH v2 8/8] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias
2015-10-03 21:11 ` [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
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