From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiCnl-0004eh-J9 for qemu-devel@nongnu.org; Fri, 02 Oct 2015 22:43:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZiCng-0007UN-I1 for qemu-devel@nongnu.org; Fri, 02 Oct 2015 22:43:57 -0400 Received: from smtpbg299.qq.com ([184.105.67.99]:47511) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiCng-0007G1-9U for qemu-devel@nongnu.org; Fri, 02 Oct 2015 22:43:52 -0400 Sender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com Date: Sat, 3 Oct 2015 10:43:07 +0800 Message-Id: <1443840187-24177-1-git-send-email-gang.chen.5i5j@gmail.com> Subject: [Qemu-devel] [PATCH] target-tilegx: Implement v2mults instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, rth@twiddle.net Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang From: Chen Gang Just according to v1multu instruction implementation. Signed-off-by: Chen Gang --- target-tilegx/helper.h | 1 + target-tilegx/simd_helper.c | 13 +++++++++++++ target-tilegx/translate.c | 5 +++++ 3 files changed, 19 insertions(+) diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 3f4fa3c..ff280ac 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -16,6 +16,7 @@ DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2mults, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index 6fa6318..4f226eb 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -41,6 +41,19 @@ uint64_t helper_v1multu(uint64_t a, uint64_t b) return r; } +uint64_t helper_v2mults(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 16) { + int64_t ae = (int16_t)(a >> i); + int64_t be = (int16_t)(b >> i); + r |= ((ae * be) & 0xffff) << i; + } + return r; +} + uint64_t helper_v1shl(uint64_t a, uint64_t b) { uint64_t m; diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 6853628..40f9b12 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -990,6 +990,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, mnemonic = "fsingle_mul1"; break; case OE_RRR(FSINGLE_MUL2, 0, X0): + tcg_gen_mov_i64(TDEST, tsrca); mnemonic = "fsingle_mul2"; break; case OE_RRR(FSINGLE_PACK2, 0, X0): @@ -1429,7 +1430,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V2MNZ, 0, X1): case OE_RRR(V2MULFSC, 0, X0): case OE_RRR(V2MULS, 0, X0): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2MULTS, 0, X0): + gen_helper_v2mults(TDEST, tsrca, tsrcb); + mnemonic = "v2shl"; + break; case OE_RRR(V2MZ, 0, X0): case OE_RRR(V2MZ, 0, X1): case OE_RRR(V2PACKH, 0, X0): -- 1.9.3