From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSS-0004rl-GO for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZiVSR-0006Kd-Gh for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:12 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:33017) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSR-0006KV-Ba for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:11 -0400 Received: by pacex6 with SMTP id ex6so139079508pac.0 for ; Sat, 03 Oct 2015 15:39:11 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 3 Oct 2015 15:38:54 -0700 Message-Id: <1443911939-2825-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> References: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v3 4/9] target-arm: Avoid inline for get_phys_addr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Avoid inline for get_phys_addr() to prepare for future recursive use. Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 610f1b5..cbc1570 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -15,10 +15,10 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #ifndef CONFIG_USER_ONLY -static inline bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr); +static bool get_phys_addr(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, uint32_t *fsr); /* Definitions for the PMCCNTR and PMCR registers */ #define PMCRD 0x8 @@ -6972,10 +6972,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, * @page_size: set to the size of the page containing phys_ptr * @fsr: set to the DFSR/IFSR value on failure */ -static inline bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr) +static bool get_phys_addr(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, uint32_t *fsr) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { /* TODO: when we support EL2 we should here call ourselves recursively -- 1.9.1