From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSb-00058k-CO for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZiVSa-0006Mc-BM for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:21 -0400 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]:34698) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSa-0006MT-6j for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:20 -0400 Received: by padhy16 with SMTP id hy16so138910373pad.1 for ; Sat, 03 Oct 2015 15:39:19 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 3 Oct 2015 15:38:58 -0700 Message-Id: <1443911939-2825-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> References: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/op_helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index d4715f4..2ccd1c9 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -90,13 +90,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t syn, exc; - bool same_el = (arm_current_el(env) != 0); + unsigned int target_el; + bool same_el; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } + target_el = exception_target_el(env); + if (fi.stage2) { + target_el = 2; + } + same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */ syn = fsr & ~(1 << 9); @@ -116,7 +122,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, env->exception.vaddress = addr; env->exception.fsr = fsr; - raise_exception(env, exc, syn, exception_target_el(env)); + raise_exception(env, exc, syn, target_el); } } #endif -- 1.9.1