From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Andreas Färber" <afaerber@suse.de>,
"Chen Fan" <chen.fan.fnst@cn.fujitsu.com>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PULL 09/12] apic: move APIC's MMIO region mapping into APIC
Date: Mon, 5 Oct 2015 13:06:31 -0300 [thread overview]
Message-ID: <1444061194-32753-10-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1444061194-32753-1-git-send-email-ehabkost@redhat.com>
From: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
When ICC bus/bridge is removed, APIC MMIO will be left
unmapped since it was mapped into system's address space
indirectly by ICC bridge.
Fix it by moving mapping into APIC code, so it would be
possible to remove ICC bus/bridge code later.
Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 7 -------
hw/intc/apic_common.c | 6 ------
target-i386/cpu.c | 15 +++++++++++++++
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 01eefa3..6a20e16 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1158,13 +1158,6 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
object_unref(OBJECT(cpu));
}
- /* map APIC MMIO area if CPU has APIC */
- if (cpu && cpu->apic_state) {
- /* XXX: what if the base changes? */
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
- APIC_DEFAULT_ADDRESS, 0x1000);
- }
-
/* tell smbios about cpuid version and features */
smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
}
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 0032b97..c0b32eb 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -296,7 +296,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
APICCommonClass *info;
static DeviceState *vapic;
static int apic_no;
- static bool mmio_registered;
if (apic_no >= MAX_APICS) {
error_setg(errp, "%s initialization failed.",
@@ -307,11 +306,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
info = APIC_COMMON_GET_CLASS(s);
info->realize(dev, errp);
- if (!mmio_registered) {
- ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));
- memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
- mmio_registered = true;
- }
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 21bad59..dba77d3 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2758,15 +2758,30 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
/* TODO: convert to link<> */
apic = APIC_COMMON(cpu->apic_state);
apic->cpu = cpu;
+ apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
}
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
+ APICCommonState *apic;
+ static bool apic_mmio_map_once;
+
if (cpu->apic_state == NULL) {
return;
}
object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
errp);
+
+ /* Map APIC MMIO area */
+ apic = APIC_COMMON(cpu->apic_state);
+ if (!apic_mmio_map_once) {
+ memory_region_add_subregion_overlap(get_system_memory(),
+ apic->apicbase &
+ MSR_IA32_APICBASE_BASE,
+ &apic->io_memory,
+ 0x1000);
+ apic_mmio_map_once = true;
+ }
}
static void x86_cpu_machine_done(Notifier *n, void *unused)
--
2.1.0
next prev parent reply other threads:[~2015-10-05 16:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 16:06 [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05 Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 01/12] cpu: Introduce X86CPUTopoInfo structure for argument simplification Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 02/12] vl: Add another sanity check to smp_parse() function Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 03/12] target-i386: Convert kvm_default_*features to property/value pairs Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 04/12] target-i386: Move breakpoint related functions to new file Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 05/12] target-i386: Make check_hw_breakpoints static Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 06/12] target-i386: get/put MSR_TSC_AUX across reset and migration Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 07/12] target-i386: add ABM to Haswell* and Broadwell* CPU models Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 08/12] Correctly re-init EFER state during INIT IPI Eduardo Habkost
2015-10-05 16:06 ` Eduardo Habkost [this message]
2015-10-05 16:06 ` [Qemu-devel] [PULL 10/12] x86: use new method to correct reset sequence Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 11/12] cpu/apic: drop icc bus/bridge Eduardo Habkost
2015-10-05 16:06 ` [Qemu-devel] [PULL 12/12] icc_bus: drop the unused files Eduardo Habkost
2015-10-06 13:47 ` [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05 Peter Maydell
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