From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zj8IJ-0006HC-KZ for qemu-devel@nongnu.org; Mon, 05 Oct 2015 12:07:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zj8IF-0005wE-Fq for qemu-devel@nongnu.org; Mon, 05 Oct 2015 12:07:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47420) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zj8IF-0005wA-7f for qemu-devel@nongnu.org; Mon, 05 Oct 2015 12:07:15 -0400 From: Eduardo Habkost Date: Mon, 5 Oct 2015 13:06:31 -0300 Message-Id: <1444061194-32753-10-git-send-email-ehabkost@redhat.com> In-Reply-To: <1444061194-32753-1-git-send-email-ehabkost@redhat.com> References: <1444061194-32753-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PULL 09/12] apic: move APIC's MMIO region mapping into APIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Chen Fan , Richard Henderson From: Chen Fan When ICC bus/bridge is removed, APIC MMIO will be left unmapped since it was mapped into system's address space indirectly by ICC bridge. Fix it by moving mapping into APIC code, so it would be possible to remove ICC bus/bridge code later. Signed-off-by: Chen Fan Signed-off-by: Zhu Guihua Reviewed-by: Igor Mammedov Signed-off-by: Eduardo Habkost --- hw/i386/pc.c | 7 ------- hw/intc/apic_common.c | 6 ------ target-i386/cpu.c | 15 +++++++++++++++ 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 01eefa3..6a20e16 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1158,13 +1158,6 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) object_unref(OBJECT(cpu)); } - /* map APIC MMIO area if CPU has APIC */ - if (cpu && cpu->apic_state) { - /* XXX: what if the base changes? */ - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, - APIC_DEFAULT_ADDRESS, 0x1000); - } - /* tell smbios about cpuid version and features */ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); } diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 0032b97..c0b32eb 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -296,7 +296,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp) APICCommonClass *info; static DeviceState *vapic; static int apic_no; - static bool mmio_registered; if (apic_no >= MAX_APICS) { error_setg(errp, "%s initialization failed.", @@ -307,11 +306,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp) info = APIC_COMMON_GET_CLASS(s); info->realize(dev, errp); - if (!mmio_registered) { - ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev)); - memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); - mmio_registered = true; - } /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 21bad59..dba77d3 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2758,15 +2758,30 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) /* TODO: convert to link<> */ apic = APIC_COMMON(cpu->apic_state); apic->cpu = cpu; + apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; } static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { + APICCommonState *apic; + static bool apic_mmio_map_once; + if (cpu->apic_state == NULL) { return; } object_property_set_bool(OBJECT(cpu->apic_state), true, "realized", errp); + + /* Map APIC MMIO area */ + apic = APIC_COMMON(cpu->apic_state); + if (!apic_mmio_map_once) { + memory_region_add_subregion_overlap(get_system_memory(), + apic->apicbase & + MSR_IA32_APICBASE_BASE, + &apic->io_memory, + 0x1000); + apic_mmio_map_once = true; + } } static void x86_cpu_machine_done(Notifier *n, void *unused) -- 2.1.0