From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjYCy-0000YV-3S for qemu-devel@nongnu.org; Tue, 06 Oct 2015 15:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjYCv-00036b-Dg for qemu-devel@nongnu.org; Tue, 06 Oct 2015 15:47:32 -0400 Received: from mail-io0-f169.google.com ([209.85.223.169]:33841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjYCv-00036U-9U for qemu-devel@nongnu.org; Tue, 06 Oct 2015 15:47:29 -0400 Received: by iow1 with SMTP id 1so197884976iow.1 for ; Tue, 06 Oct 2015 12:47:28 -0700 (PDT) From: Davorin Mista Date: Tue, 6 Oct 2015 12:47:20 -0700 Message-Id: <1444160840-16439-1-git-send-email-davorin.mista@aggios.com> Subject: [Qemu-devel] [PATCHv4] target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Davorin Mista , peter.maydell@linaro.org, edgari@xilinx.com, alistai@xilinx.com, sorenb@xilinx.com Added oslar_write function to OSLAR_EL1 sysreg, using a status variable in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked to the newly added read-only OSLSR_EL1 register. Linux reads from this register during its suspend/resume procedure. Signed-off-by: Davorin Mista --- Changed in v2: -switched from using dummy registers to an actual register implementation -implemented write function for OSLAR_EL1 sysreg -added state variable to ARMCPUState struct Changed in v3: -renamed variable to oslsr_el1 and moved to cp15 -renamed write frunction to oslar_write -support both 32bit and 64bit ARM in oslar_write -moved resetvalue to the corresponding read-only register -removed "dummy" comments above registers Changed in v4: -added type = ARM_CP_NO_RAW -removed fieldOffset for OSLAR register -tested with QEMU mainline (git.qemu.org/qemu.git) --- target-arm/cpu.h | 1 + target-arm/helper.c | 22 ++++++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cc1578c..9b80c26 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -378,6 +378,7 @@ typedef struct CPUARMState { uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ uint64_t mdscr_el1; + uint64_t oslsr_el1; /* OS Lock Status */ /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 8367997..33a3e3f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3564,6 +3564,20 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) return CP_ACCESS_OK; } +/* write to oslsr_el1 (OS lock status) state variable */ +static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + int oslock; + + if (ri->state == ARM_CP_STATE_AA32) { + oslock = (value == 0xC5ACCE55); + } else { + oslock = value & 1; + } + + env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); +} + static const ARMCPRegInfo debug_cp_reginfo[] = { /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; @@ -3592,10 +3606,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .type = ARM_CP_ALIAS, .access = PL1_R, .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, - /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, - .access = PL1_W, .type = ARM_CP_NOP }, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = oslar_write }, + { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, + .access = PL1_R, .resetvalue = 10, + .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, /* Dummy OSDLR_EL1: 32-bit Linux will read this */ { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, -- 2.6.0