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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Chen Gang <gang.chen.5i5j@gmail.com>
Subject: [Qemu-devel] [PULL 08/19] target-tilegx: Let x1 pipe process bpt instruction only
Date: Wed,  7 Oct 2015 20:33:06 +1100	[thread overview]
Message-ID: <1444210397-20679-9-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1444210397-20679-1-git-send-email-rth@twiddle.net>

From: Chen Gang <gang.chen.5i5j@gmail.com>

According to the related document, bpt can be only in x1 pipe.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-tilegx/translate.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index d7e4d52..3566b88 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -458,8 +458,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
         mnemonic = "flushwb";
         goto done0;
     case OE_RR_X1(ILL):
+        if (dest == 0x1c && srca == 0x25) {
+            mnemonic = "bpt";
+            goto done2;
+        }
+        /* Fall through */
     case OE_RR_Y1(ILL):
-        mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
+        mnemonic = "ill";
+    done2:
         qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
         return TILEGX_EXCP_OPCODE_UNKNOWN;
     case OE_RR_X1(MF):
-- 
2.4.3

  parent reply	other threads:[~2015-10-07  9:33 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-07  9:32 [Qemu-devel] [PULL 00/19] Collected tilegx patches Richard Henderson
2015-10-07  9:32 ` [Qemu-devel] [PULL 01/19] target-tilegx: Tidy simd_helper.c Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 02/19] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 03/19] target-tilegx: Implement v*add and v*sub instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 04/19] target-tilegx: Implement v1multu instruction Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 05/19] target-tilegx: Implement crc instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 06/19] target-tilegx: Implement table index instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 07/19] target-tilegx: Implement complex multiply instructions Richard Henderson
2015-10-07  9:33 ` Richard Henderson [this message]
2015-10-07  9:33 ` [Qemu-devel] [PULL 09/19] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 11/19] target-tilegx: Decode ill pseudo-instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 12/19] target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 13/19] target-tilegx: Fix a typo for mnemonic about "ld_add" Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 14/19] target-tilegx: Handle nofault prefetch instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 15/19] target-tilegx: Implement v2sh* instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 16/19] target-tilegx: Implement v?int_* instructions Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 17/19] target-tilegx: Implement v2mults instruction Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 18/19] target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly Richard Henderson
2015-10-07  9:33 ` [Qemu-devel] [PULL 19/19] target-tilegx: Support iret instruction and related special registers Richard Henderson
2015-10-08 13:18 ` [Qemu-devel] [PULL 00/19] Collected tilegx patches Peter Maydell

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