From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjlGk-0001af-CF for qemu-devel@nongnu.org; Wed, 07 Oct 2015 05:44:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjlGj-0004HU-Il for qemu-devel@nongnu.org; Wed, 07 Oct 2015 05:44:18 -0400 Received: from mail-pa0-x231.google.com ([2607:f8b0:400e:c03::231]:33806) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjlGj-0004HN-DG for qemu-devel@nongnu.org; Wed, 07 Oct 2015 05:44:17 -0400 Received: by padhy16 with SMTP id hy16so16772716pad.1 for ; Wed, 07 Oct 2015 02:44:17 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 7 Oct 2015 20:43:31 +1100 Message-Id: <1444211031-11624-7-git-send-email-rth@twiddle.net> In-Reply-To: <1444211031-11624-1-git-send-email-rth@twiddle.net> References: <1444211031-11624-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 06/26] target-arm: Add condexec state to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Reviewed-by: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-arm/cpu.h | 1 + target-arm/translate-a64.c | 2 +- target-arm/translate.c | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cc1578c..cebd463 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -95,6 +95,7 @@ struct arm_boot_info; #define NB_MMU_MODES 7 +#define TARGET_INSN_START_EXTRA_WORDS 1 /* We currently assume float and double are IEEE single and double precision respectively. diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index bc2040e..654a586 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11090,7 +11090,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->pc, 0); num_insns++; if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { diff --git a/target-arm/translate.c b/target-arm/translate.c index 44468dc..fb69ecb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11317,7 +11317,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1)); num_insns++; #ifdef CONFIG_USER_ONLY -- 2.4.3