From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkUD5-00068C-JM for qemu-devel@nongnu.org; Fri, 09 Oct 2015 05:43:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZkUD2-0005Zy-Cf for qemu-devel@nongnu.org; Fri, 09 Oct 2015 05:43:31 -0400 Received: from mail-lb0-x22c.google.com ([2a00:1450:4010:c04::22c]:36653) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkUD2-0005Zu-5I for qemu-devel@nongnu.org; Fri, 09 Oct 2015 05:43:28 -0400 Received: by lbcao8 with SMTP id ao8so75393950lbc.3 for ; Fri, 09 Oct 2015 02:43:27 -0700 (PDT) From: Sergey Fedorov Date: Fri, 9 Oct 2015 12:43:14 +0300 Message-Id: <1444383794-16767-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH v2] target-arm: Add MDCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Sergey Fedorov , Peter Maydell Signed-off-by: Sergey Fedorov --- Changes in v2: * Reset value is simply made zero target-arm/cpu.h | 1 + target-arm/helper.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cc1578c..51d8ed1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -378,6 +378,7 @@ typedef struct CPUARMState { uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ uint64_t mdscr_el1; + uint64_t mdcr_el2; /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 8367997..ec4097b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3223,6 +3223,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -3576,6 +3579,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* The only field of MDCR_EL2 that has a defined architectural reset value + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we + * don't impelment any PMU event counters, so using zero as a reset + * value for MDCR_EL2 is okay */ + { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL2_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ -- 1.9.1