From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlkaB-0004lJ-3r for qemu-devel@nongnu.org; Mon, 12 Oct 2015 17:24:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZlkaA-0001H0-C0 for qemu-devel@nongnu.org; Mon, 12 Oct 2015 17:24:35 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:34086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlkaA-0001Gs-73 for qemu-devel@nongnu.org; Mon, 12 Oct 2015 17:24:34 -0400 Received: by padhy16 with SMTP id hy16so163416639pad.1 for ; Mon, 12 Oct 2015 14:24:33 -0700 (PDT) Received: from bigtime.com ([101.191.203.214]) by smtp.gmail.com with ESMTPSA id zc4sm20083274pbb.24.2015.10.12.14.24.32 for (version=TLSv1/SSLv3 cipher=OTHER); Mon, 12 Oct 2015 14:24:33 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 13 Oct 2015 08:23:48 +1100 Message-Id: <1444685028-4950-4-git-send-email-rth@twiddle.net> In-Reply-To: <1444685028-4950-1-git-send-email-rth@twiddle.net> References: <1444685028-4950-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/3] tcg/ppc: Prefer mask over andi. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Prefer the instruction that isn't required to modify cr0. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index cee13e0..2c72565 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -700,14 +700,14 @@ static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) { int mb, me; - if ((c & 0xffff) == c) { + if (mask_operand(c, &mb, &me)) { + tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); + } else if ((c & 0xffff) == c) { tcg_out32(s, ANDI | SAI(src, dst, c)); return; } else if ((c & 0xffff0000) == c) { tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); return; - } else if (mask_operand(c, &mb, &me)) { - tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); } else { tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); @@ -719,18 +719,18 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) int mb, me; assert(TCG_TARGET_REG_BITS == 64); - if ((c & 0xffff) == c) { - tcg_out32(s, ANDI | SAI(src, dst, c)); - return; - } else if ((c & 0xffff0000) == c) { - tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); - return; - } else if (mask64_operand(c, &mb, &me)) { + if (mask64_operand(c, &mb, &me)) { if (mb == 0) { tcg_out_rld(s, RLDICR, dst, src, 0, me); } else { tcg_out_rld(s, RLDICL, dst, src, 0, mb); } + } else if ((c & 0xffff) == c) { + tcg_out32(s, ANDI | SAI(src, dst, c)); + return; + } else if ((c & 0xffff0000) == c) { + tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); + return; } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); -- 2.4.3