From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlwK4-0000Hh-PR for qemu-devel@nongnu.org; Tue, 13 Oct 2015 05:56:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZlwK3-0006yQ-5j for qemu-devel@nongnu.org; Tue, 13 Oct 2015 05:56:44 -0400 Received: from mail-lb0-x22f.google.com ([2a00:1450:4010:c04::22f]:33617) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlwK2-0006xy-R7 for qemu-devel@nongnu.org; Tue, 13 Oct 2015 05:56:43 -0400 Received: by lbbk10 with SMTP id k10so13518785lbb.0 for ; Tue, 13 Oct 2015 02:56:42 -0700 (PDT) From: Sergey Fedorov Date: Tue, 13 Oct 2015 12:56:28 +0300 Message-Id: <1444730188-5861-3-git-send-email-serge.fdrv@gmail.com> In-Reply-To: <1444730188-5861-1-git-send-email-serge.fdrv@gmail.com> References: <1444730188-5861-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH v3 2/2] target-arm: Fix CPU breakpoint handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Sergey Fedorov , Peter Maydell A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exception handler. Generate a call to a helper to check CPU breakpoints and raise an exception only if any breakpoint matches architecturally. Signed-off-by: Sergey Fedorov --- target-arm/helper.h | 2 ++ target-arm/op_helper.c | 29 ++++++++++++++++++----------- target-arm/translate-a64.c | 17 ++++++++++++----- target-arm/translate.c | 19 ++++++++++++++----- 4 files changed, 46 insertions(+), 21 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index 827b33d..c2a85c7 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -54,6 +54,8 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(check_breakpoints, void, env) + DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 67b18c0..7929c71 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -867,6 +867,15 @@ static bool check_breakpoints(ARMCPU *cpu) return false; } +void HELPER(check_breakpoints)(CPUARMState *env) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (check_breakpoints(cpu)) { + HELPER(exception_internal(env, EXCP_DEBUG)); + } +} + void arm_debug_excp_handler(CPUState *cs) { /* Called by core code when a watchpoint or breakpoint fires; @@ -898,23 +907,21 @@ void arm_debug_excp_handler(CPUState *cs) } } else { uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; + bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); if (cpu_breakpoint_test(cs, pc, BP_GDB)) { return; } - if (check_breakpoints(cpu)) { - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); - if (extended_addresses_enabled(env)) { - env->exception.fsr = (1 << 9) | 0x22; - } else { - env->exception.fsr = 0x2; - } - /* FAR is UNKNOWN, so doesn't need setting */ - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), - arm_debug_target_el(env)); + if (extended_addresses_enabled(env)) { + env->exception.fsr = (1 << 9) | 0x22; + } else { + env->exception.fsr = 0x2; } + /* FAR is UNKNOWN, so doesn't need setting */ + raise_exception(env, EXCP_PREFETCH_ABORT, + syn_breakpoint(same_el), + arm_debug_target_el(env)); } } diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e65e309..09a5dde 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11084,11 +11084,18 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* Advance PC so that clearing the breakpoint will - invalidate this TB. */ - dc->pc += 2; - goto done_generating; + if (bp->flags & BP_CPU) { + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->is_jmp = DISAS_UPDATE; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* Advance PC so that clearing the breakpoint will + invalidate this TB. */ + dc->pc += 4; + goto done_generating; + } + break; } } } diff --git a/target-arm/translate.c b/target-arm/translate.c index 22c3587..0652721 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11329,11 +11329,20 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* Advance PC so that clearing the breakpoint will - invalidate this TB. */ - dc->pc += 2; - goto done_generating; + if (bp->flags & BP_CPU) { + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->is_jmp = DISAS_UPDATE; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* Advance PC so that clearing the breakpoint will + invalidate this TB. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc += 2; + goto done_generating; + } + break; } } } -- 1.9.1