From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmckJ-0007vD-SO for qemu-devel@nongnu.org; Thu, 15 Oct 2015 03:14:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZmckF-0005YC-RE for qemu-devel@nongnu.org; Thu, 15 Oct 2015 03:14:39 -0400 Received: from mail-bn1bon0092.outbound.protection.outlook.com ([157.56.111.92]:56352 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmckF-0005XQ-Js for qemu-devel@nongnu.org; Thu, 15 Oct 2015 03:14:35 -0400 From: Soren Brinkmann Date: Wed, 14 Oct 2015 21:41:08 -0700 Message-ID: <1444884068-22718-1-git-send-email-soren.brinkmann@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH QEMU] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Soren Brinkmann Signed-off-by: Soren Brinkmann --- Hi, I recently came across some code that caused undefined instruction exceptio= ns when executing instructions 'mrs x11, spsr_abt' and the like. I'm not s= ure I get the full picture, but it seems QEMU already keeps the state for those S= PSR registers and all that might be missing is exposing those registers to the guest. Thanks, S=C3=B6ren target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 83679970b432..0c64c0588115 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3281,6 +3281,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_sp= sr[6]) }, + { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_sp= sr[4]) }, + { .name =3D "SPSR_ABT", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_sp= sr[2]) }, + { .name =3D "SPSR_UND", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 2, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_sp= sr[3]) }, + { .name =3D "SPSR_FIQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_sp= sr[5]) }, { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vbar_write, --=20 2.6.1.3.g59394a9