From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZoEQA-0004oW-Is for qemu-devel@nongnu.org; Mon, 19 Oct 2015 13:40:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZoEQ7-00054w-TN for qemu-devel@nongnu.org; Mon, 19 Oct 2015 13:40:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34437) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZoEQ7-00054s-O0 for qemu-devel@nongnu.org; Mon, 19 Oct 2015 13:40:27 -0400 From: Eduardo Habkost Date: Mon, 19 Oct 2015 15:40:04 -0200 Message-Id: <1445276410-5031-4-git-send-email-ehabkost@redhat.com> In-Reply-To: <1445276410-5031-1-git-send-email-ehabkost@redhat.com> References: <1445276410-5031-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PATCH v3 3/9] target-i386: Ensure bit 10 on DR7 is never cleared List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Paolo Bonzini , Richard Henderson Bit 10 of DR7 is documented as always set to 1, so ensure that's always the case. Signed-off-by: Eduardo Habkost --- Changes series v2 -> series v3: * Set bit on new_dr7, so that it can still pass the xor test for the enable bits optimization * Suggested-by: Richard Henderson --- target-i386/bpt_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c index 23ce828..49472ea 100644 --- a/target-i386/bpt_helper.c +++ b/target-i386/bpt_helper.c @@ -85,6 +85,8 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7) target_ulong old_dr7 = env->dr[7]; int i; + new_dr7 |= DR7_FIXED_1; + /* If nothing is changing except the global/local enable bits, then we can make the change more efficient. */ if (((old_dr7 ^ new_dr7) & ~0xff) == 0) { -- 2.1.0