From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zp1Ap-0000zB-HB for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zp1Ao-0001P2-G9 for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:55 -0400 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:36825) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zp1Ao-0001Oy-C7 for qemu-devel@nongnu.org; Wed, 21 Oct 2015 17:43:54 -0400 Received: by qgad10 with SMTP id d10so40182144qga.3 for ; Wed, 21 Oct 2015 14:43:54 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 21 Oct 2015 11:42:55 -1000 Message-Id: <1445463779-5823-7-git-send-email-rth@twiddle.net> In-Reply-To: <1445463779-5823-1-git-send-email-rth@twiddle.net> References: <1445463779-5823-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 06/10] tcg/mips: Add use_mips32r6_instructions definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, James Hogan From: James Hogan Add definition use_mips32r6_instructions to the MIPS TCG backend which is constant 1 when built for MIPS release 6. This will be used to decide between pre-R6 and R6 instruction encodings. Reviewed-by: Aurelien Jarno Signed-off-by: James Hogan Signed-off-by: Richard Henderson Message-Id: <1443788657-14537-4-git-send-email-james.hogan@imgtec.com> --- tcg/mips/tcg-target.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index f5ba52c..e579c10 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -96,6 +96,13 @@ extern bool use_mips32_instructions; extern bool use_mips32r2_instructions; #endif +/* MIPS32R6 instruction set detection */ +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) +#define use_mips32r6_instructions 1 +#else +#define use_mips32r6_instructions 0 +#endif + /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 -- 2.4.3