* [Qemu-devel] [PATCH qemu 0/2] ppc: Add "ibm,pa-features" @ 2015-10-22 7:30 Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 1/2] ppc: Add mmu_model defines for arch 2.03 and 2.07 Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree Alexey Kardashevskiy 0 siblings, 2 replies; 4+ messages in thread From: Alexey Kardashevskiy @ 2015-10-22 7:30 UTC (permalink / raw) To: qemu-devel; +Cc: Alexey Kardashevskiy, qemu-ppc, Alexander Graf, David Gibson This adds an "ibm,pa-features" property. Please comment. Thanks. Benjamin Herrenschmidt (2): ppc: Add mmu_model defines for arch 2.03 and 2.07 ppc/spapr: Add "ibm,pa-features" property to the device-tree hw/ppc/spapr.c | 31 +++++++++++++++++++++++++++++++ target-ppc/cpu.h | 11 ++++++----- target-ppc/kvm.c | 15 ++++++++++++--- target-ppc/mmu_helper.c | 16 ++++++++-------- target-ppc/translate.c | 4 ++-- target-ppc/translate_init.c | 5 +++-- 6 files changed, 62 insertions(+), 20 deletions(-) -- 2.5.0.rc3 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH qemu 1/2] ppc: Add mmu_model defines for arch 2.03 and 2.07 2015-10-22 7:30 [Qemu-devel] [PATCH qemu 0/2] ppc: Add "ibm,pa-features" Alexey Kardashevskiy @ 2015-10-22 7:30 ` Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree Alexey Kardashevskiy 1 sibling, 0 replies; 4+ messages in thread From: Alexey Kardashevskiy @ 2015-10-22 7:30 UTC (permalink / raw) To: qemu-devel; +Cc: Alexey Kardashevskiy, qemu-ppc, Alexander Graf, David Gibson From: Benjamin Herrenschmidt <benh@kernel.crashing.org> This removes unused POWERPC_MMU_2_06a/POWERPC_MMU_2_06d. This replaces POWERPC_MMU_64B with POWERPC_MMU_2_03 for POWER5+ to be more explicit about the version of the PowerISA supported. This defines POWERPC_MMU_2_07 and uses it for the POWER8 CPU family. This will not have an immediate effect now but it will in the following patch. This should cause no behavioural change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- target-ppc/cpu.h | 10 +++++----- target-ppc/kvm.c | 8 +++++--- target-ppc/mmu_helper.c | 16 ++++++++-------- target-ppc/translate.c | 4 ++-- target-ppc/translate_init.c | 4 ++-- 5 files changed, 22 insertions(+), 20 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 98ce5a7..69d8cf6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -117,14 +117,14 @@ enum powerpc_mmu_t { #define POWERPC_MMU_AMR 0x00040000 /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, + /* Architecture 2.03 and later (has LPCR) */ + POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ - POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ - POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, + /* Architecture 2.07 variant */ + POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_AMR | 0x00000004, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 38aa927..7671ae7 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -259,7 +259,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->flags |= KVM_PPC_1T_SEGMENTS; } - if (env->mmu_model == POWERPC_MMU_2_06) { + if (env->mmu_model == POWERPC_MMU_2_06 || + env->mmu_model == POWERPC_MMU_2_07) { info->slb_size = 32; } else { info->slb_size = 64; @@ -272,8 +273,9 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->sps[i].enc[0].pte_enc = 0; i++; - /* 64K on MMU 2.06 */ - if (env->mmu_model == POWERPC_MMU_2_06) { + /* 64K on MMU 2.06 and later */ + if (env->mmu_model == POWERPC_MMU_2_06 || + env->mmu_model == POWERPC_MMU_2_07) { info->sps[i].page_shift = 16; info->sps[i].slb_enc = 0x110; info->sps[i].enc[0].page_shift = 16; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 527c6ad..e52d0e5 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1293,9 +1293,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: dump_slb(f, cpu_fprintf, env); break; #endif @@ -1433,9 +1433,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) switch (env->mmu_model) { #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1937,9 +1937,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_601: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: #endif /* defined(TARGET_PPC64) */ tlb_flush(CPU(cpu), 1); break; @@ -2011,9 +2011,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c2bc1a7..453509a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11327,9 +11327,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_06d: + case POWERPC_MMU_2_07: #endif cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b541473..2adbb63 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8019,7 +8019,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; + pcc->mmu_model = POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif @@ -8243,7 +8243,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_2_06; + pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; #endif -- 2.5.0.rc3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree 2015-10-22 7:30 [Qemu-devel] [PATCH qemu 0/2] ppc: Add "ibm,pa-features" Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 1/2] ppc: Add mmu_model defines for arch 2.03 and 2.07 Alexey Kardashevskiy @ 2015-10-22 7:30 ` Alexey Kardashevskiy 2015-11-26 15:07 ` Alexander Graf 1 sibling, 1 reply; 4+ messages in thread From: Alexey Kardashevskiy @ 2015-10-22 7:30 UTC (permalink / raw) To: qemu-devel; +Cc: Alexey Kardashevskiy, qemu-ppc, Alexander Graf, David Gibson From: Benjamin Herrenschmidt <benh@kernel.crashing.org> LoPAPR defines a "ibm,pa-features" per-CPU device tree property which describes extended features of the Processor Architecture. This adds the property to the device tree. At the moment this is the copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" which is enabled for TCG and disabled when running under HV KVM host with 4K system page size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log, moved ci_large_pages initialization, renamed pa_features arrays] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- hw/ppc/spapr.c | 31 +++++++++++++++++++++++++++++++ target-ppc/cpu.h | 1 + target-ppc/kvm.c | 7 +++++++ target-ppc/translate_init.c | 1 + 4 files changed, 40 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3852ad1..21c1312 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -597,6 +597,24 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, uint32_t vcpus_per_socket = smp_threads * smp_cores; uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; + /* Note: we keep CI large pages off for now because a 64K capable guest + * provisioned with large pages might otherwise try to map a qemu + * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages + * even if that qemu runs on a 4k host. + * + * We can later add this bit back when we are confident this is not + * an issue (!HV KVM or 64K host) + */ + uint8_t pa_features_206[] = { 6, 0, + 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; + uint8_t pa_features_207[] = { 24, 0, + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; + uint8_t *pa_features; + size_t pa_size; + _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); @@ -662,6 +680,19 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, page_sizes_prop, page_sizes_prop_size))); } + /* Do the ibm,pa-features property, adjust it for ci-large-pages */ + if (env->mmu_model == POWERPC_MMU_2_06) { + pa_features = pa_features_206; + pa_size = sizeof(pa_features_206); + } else /* env->mmu_model == POWERPC_MMU_2_07 */ { + pa_features = pa_features_207; + pa_size = sizeof(pa_features_207); + } + if (env->ci_large_pages) { + pa_features[3] |= 0x20; + } + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 69d8cf6..b34aed6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1073,6 +1073,7 @@ struct CPUPPCState { uint64_t insns_flags2; #if defined(TARGET_PPC64) struct ppc_segment_page_sizes sps; + bool ci_large_pages; #endif #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 7671ae7..0c59f7f 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -414,6 +414,13 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) /* Convert to QEMU form */ memset(&env->sps, 0, sizeof(env->sps)); + /* If we have HV KVM, we need to forbid CI large pages if our + * host page size is smaller than 64K. + */ + if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) { + env->ci_large_pages = getpagesize() >= 0x10000; + } + /* * XXX This loop should be an entry wide AND of the capabilities that * the selected CPU has with the capabilities that KVM supports. diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 2adbb63..4934c80 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7864,6 +7864,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_book3s_ids(env); gen_spr_amr(env); gen_spr_book3s_purr(env); + env->ci_large_pages = true; break; default: g_assert_not_reached(); -- 2.5.0.rc3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree Alexey Kardashevskiy @ 2015-11-26 15:07 ` Alexander Graf 0 siblings, 0 replies; 4+ messages in thread From: Alexander Graf @ 2015-11-26 15:07 UTC (permalink / raw) To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, David Gibson On 22.10.15 09:30, Alexey Kardashevskiy wrote: > From: Benjamin Herrenschmidt <benh@kernel.crashing.org> > > LoPAPR defines a "ibm,pa-features" per-CPU device tree property which > describes extended features of the Processor Architecture. > > This adds the property to the device tree. At the moment this is the > copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" > which is enabled for TCG and disabled when running under HV KVM host > with 4K system page size. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > [aik: rebased, changed commit log, moved ci_large_pages initialization, > renamed pa_features arrays] > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> > --- > hw/ppc/spapr.c | 31 +++++++++++++++++++++++++++++++ > target-ppc/cpu.h | 1 + > target-ppc/kvm.c | 7 +++++++ > target-ppc/translate_init.c | 1 + > 4 files changed, 40 insertions(+) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 3852ad1..21c1312 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -597,6 +597,24 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, > uint32_t vcpus_per_socket = smp_threads * smp_cores; > uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; > > + /* Note: we keep CI large pages off for now because a 64K capable guest > + * provisioned with large pages might otherwise try to map a qemu > + * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages > + * even if that qemu runs on a 4k host. > + * > + * We can later add this bit back when we are confident this is not > + * an issue (!HV KVM or 64K host) > + */ > + uint8_t pa_features_206[] = { 6, 0, > + 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; > + uint8_t pa_features_207[] = { 24, 0, > + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, > + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; That's a lot of magic numbers. Do you think you could convert them into something slightly more readable? > + uint8_t *pa_features; > + size_t pa_size; > + > _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); > _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); > > @@ -662,6 +680,19 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, > page_sizes_prop, page_sizes_prop_size))); > } > > + /* Do the ibm,pa-features property, adjust it for ci-large-pages */ > + if (env->mmu_model == POWERPC_MMU_2_06) { > + pa_features = pa_features_206; > + pa_size = sizeof(pa_features_206); > + } else /* env->mmu_model == POWERPC_MMU_2_07 */ { > + pa_features = pa_features_207; > + pa_size = sizeof(pa_features_207); > + } > + if (env->ci_large_pages) { > + pa_features[3] |= 0x20; > + } > + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); > + > _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", > cs->cpu_index / vcpus_per_socket))); > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 69d8cf6..b34aed6 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1073,6 +1073,7 @@ struct CPUPPCState { > uint64_t insns_flags2; > #if defined(TARGET_PPC64) > struct ppc_segment_page_sizes sps; > + bool ci_large_pages; > #endif > > #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) > diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c > index 7671ae7..0c59f7f 100644 > --- a/target-ppc/kvm.c > +++ b/target-ppc/kvm.c > @@ -414,6 +414,13 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) > /* Convert to QEMU form */ > memset(&env->sps, 0, sizeof(env->sps)); > > + /* If we have HV KVM, we need to forbid CI large pages if our > + * host page size is smaller than 64K. > + */ > + if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) { > + env->ci_large_pages = getpagesize() >= 0x10000; There's a global variable for the page size, no? Alex ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-11-26 15:07 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-10-22 7:30 [Qemu-devel] [PATCH qemu 0/2] ppc: Add "ibm,pa-features" Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 1/2] ppc: Add mmu_model defines for arch 2.03 and 2.07 Alexey Kardashevskiy 2015-10-22 7:30 ` [Qemu-devel] [PATCH qemu 2/2] ppc/spapr: Add "ibm, pa-features" property to the device-tree Alexey Kardashevskiy 2015-11-26 15:07 ` Alexander Graf
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).