From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Andrew Jones" <drjones@redhat.com>,
"Andreas Färber" <afaerber@suse.de>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PULL 13/13] vl: trivial: minor tweaks to a max-cpu error msg
Date: Fri, 23 Oct 2015 13:33:12 -0200 [thread overview]
Message-ID: <1445614392-26687-14-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1445614392-26687-1-git-send-email-ehabkost@redhat.com>
From: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
---
vl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index 332d828..dffaf09 100644
--- a/vl.c
+++ b/vl.c
@@ -4101,8 +4101,8 @@ int main(int argc, char **argv, char **envp)
machine_class->max_cpus = machine_class->max_cpus ?: 1; /* Default to UP */
if (max_cpus > machine_class->max_cpus) {
- fprintf(stderr, "Number of SMP cpus requested (%d), exceeds max cpus "
- "supported by machine `%s' (%d)\n", max_cpus,
+ fprintf(stderr, "Number of SMP CPUs requested (%d) exceeds max CPUs "
+ "supported by machine '%s' (%d)\n", max_cpus,
machine_class->name, machine_class->max_cpus);
exit(1);
}
--
2.1.0
next prev parent reply other threads:[~2015-10-23 15:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-23 15:32 [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 03/13] target-i386: Introduce cpu_x86_update_dr7 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 04/13] target-i386: Re-introduce optimal breakpoint removal Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 05/13] target-i386: Ensure bit 10 on DR7 is never cleared Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 06/13] target-i386: Move hw_*breakpoint_* functions Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 07/13] target-i386: Optimize setting dr[0-3] Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 08/13] target-i386: Handle I/O breakpoints Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 09/13] target-i386: Check CR4[DE] for processing DR4/DR5 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 10/13] target-i386: Ensure always-1 bits on DR6 can't be cleared Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 11/13] target-i386: Add DE to TCG_FEATURES Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 12/13] target-i386: Use 1UL for bit shift Eduardo Habkost
2015-10-23 15:33 ` Eduardo Habkost [this message]
2015-10-23 17:14 ` [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23 Peter Maydell
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