From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56615) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpeLO-0001fS-Cg for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZpeLJ-0001hu-KH for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpeLJ-0001hi-Eo for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:21 -0400 From: Eduardo Habkost Date: Fri, 23 Oct 2015 13:33:00 -0200 Message-Id: <1445614392-26687-2-git-send-email-ehabkost@redhat.com> In-Reply-To: <1445614392-26687-1-git-send-email-ehabkost@redhat.com> References: <1445614392-26687-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Jordan Justen , qemu-devel@nongnu.org, Paolo Bonzini , Laszlo Ersek , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson From: Paolo Bonzini Processors up to the Pentium (says Bochs---I do not have old enough manuals) require a 32KiB alignment for the SMBASE, but newer processors do not need that, and Tiano Core will use non-aligned SMBASE values. Reported-by: Michael D Kinney Cc: Laszlo Ersek Cc: Jordan Justen Cc: Eduardo Habkost Signed-off-by: Paolo Bonzini Reviewed-by: Laszlo Ersek Reviewed-by: Eduardo Habkost Signed-off-by: Eduardo Habkost --- target-i386/smm_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 02e24b9..c272a98 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -266,7 +266,7 @@ void helper_rsm(CPUX86State *env) val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff; + env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00); } #else cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); @@ -319,7 +319,7 @@ void helper_rsm(CPUX86State *env) val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff; + env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) { -- 2.1.0