From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpeLO-0001es-48 for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZpeLN-0001jY-2n for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54195) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpeLM-0001jM-UE for qemu-devel@nongnu.org; Fri, 23 Oct 2015 11:33:25 -0400 From: Eduardo Habkost Date: Fri, 23 Oct 2015 13:33:01 -0200 Message-Id: <1445614392-26687-3-git-send-email-ehabkost@redhat.com> In-Reply-To: <1445614392-26687-1-git-send-email-ehabkost@redhat.com> References: <1445614392-26687-1-git-send-email-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Beno=C3=AEt=20Canet?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson The host cache information may not make sense for the guest if the VM CPU topology doesn't match the host CPU topology. To make sure we won't expose broken cache information to the guest, disable cache info passthrough by default, and add a new "host-cache-info" property that can be used to enable the old behavior for users that really need it. Cc: Beno=C3=AEt Canet Reviewed-by: Igor Mammedov Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 4 +--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c5961d7..7037de0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -318,6 +318,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint6= 4_t *); .driver =3D "Broadwell-noTSX-" TYPE_X86_CPU,\ .property =3D "abm",\ .value =3D "off",\ + },\ + {\ + .driver =3D "host" "-" TYPE_X86_CPU,\ + .property =3D "host-cache-info",\ + .value =3D "on",\ }, =20 #define PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 5f53af2..987253d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -656,7 +656,6 @@ struct X86CPUDefinition { int stepping; FeatureWordArray features; char model_id[48]; - bool cache_info_passthrough; }; =20 static X86CPUDefinition builtin_x86_defs[] =3D { @@ -1420,6 +1419,7 @@ static X86CPUDefinition host_cpudef; =20 static Property host_x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), + DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, = false), DEFINE_PROP_END_OF_LIST() }; =20 @@ -1446,7 +1446,6 @@ static void host_x86_cpu_class_init(ObjectClass *oc= , void *data) cpu_x86_fill_model_id(host_cpudef.model_id); =20 xcc->cpu_def =3D &host_cpudef; - host_cpudef.cache_info_passthrough =3D true; =20 /* level, xlevel, xlevel2, and the feature words are initialized on * instance_init, because they require KVM to be initialized. @@ -2094,7 +2093,6 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDef= inition *def, Error **errp) object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp= ); object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp); object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp); - cpu->cache_info_passthrough =3D def->cache_info_passthrough; object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp= ); for (w =3D 0; w < FEATURE_WORDS; w++) { env->features[w] =3D def->features[w]; --=20 2.1.0