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From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PULL 07/13] target-i386: Optimize setting dr[0-3]
Date: Fri, 23 Oct 2015 13:33:06 -0200	[thread overview]
Message-ID: <1445614392-26687-8-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1445614392-26687-1-git-send-email-ehabkost@redhat.com>

From: Richard Henderson <rth@twiddle.net>

If the debug register is not enabled, we need
do nothing besides update the register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target-i386/bpt_helper.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index ca58ab7..7ff41a6 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -228,9 +228,14 @@ void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 {
 #ifndef CONFIG_USER_ONLY
     if (reg < 4) {
-        hw_breakpoint_remove(env, reg);
-        env->dr[reg] = t0;
-        hw_breakpoint_insert(env, reg);
+        if (hw_breakpoint_enabled(env->dr[7], reg)
+            && hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
+            hw_breakpoint_remove(env, reg);
+            env->dr[reg] = t0;
+            hw_breakpoint_insert(env, reg);
+        } else {
+            env->dr[reg] = t0;
+        }
     } else if (reg == 7) {
         cpu_x86_update_dr7(env, t0);
     } else {
-- 
2.1.0

  parent reply	other threads:[~2015-10-23 15:33 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-23 15:32 [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 03/13] target-i386: Introduce cpu_x86_update_dr7 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 04/13] target-i386: Re-introduce optimal breakpoint removal Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 05/13] target-i386: Ensure bit 10 on DR7 is never cleared Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 06/13] target-i386: Move hw_*breakpoint_* functions Eduardo Habkost
2015-10-23 15:33 ` Eduardo Habkost [this message]
2015-10-23 15:33 ` [Qemu-devel] [PULL 08/13] target-i386: Handle I/O breakpoints Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 09/13] target-i386: Check CR4[DE] for processing DR4/DR5 Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 10/13] target-i386: Ensure always-1 bits on DR6 can't be cleared Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 11/13] target-i386: Add DE to TCG_FEATURES Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 12/13] target-i386: Use 1UL for bit shift Eduardo Habkost
2015-10-23 15:33 ` [Qemu-devel] [PULL 13/13] vl: trivial: minor tweaks to a max-cpu error msg Eduardo Habkost
2015-10-23 17:14 ` [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23 Peter Maydell

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