[Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Hi,

Another round of patches towards EL2 support. This one adds partial
support for 2-stage MMU. The AArch32/ARMv7 support is untested.

Some of the details of error reporting are intentionally missing, I
was thinking to add those incrementally as they get quite involved
(e.g the register target and memory access size).
S2 traps during while translating due to ATS writes are not handled
either.

Comments welcome!

Best regards,
Edgar

v4 -> v5:
* Avoid mixed code and vairable declaration of t0sz/t1sz
* Separate logic for AArch32 S1/S2 t0sz extraction
* Fix VTCR_EL2 typo
* Use level and startlevel more like in the ARM manuals
* Fix startlevel check logic
* Let callers of get_phys_addr update hpfar_el2

v3 -> v4:
* Introduce inputsize to simplify and better match ref manuals
* Rename granule_sz to stride to better match ref manuals
* Add support for AArch32 negative S2 t0sz
* Add support for computing the AArch32 S2 PTW starting level
* Add support for trapping on bad S2 starting levels

v2 -> v3:
* Prettify comments for ARMMMUFaultInfo
* Add S2 translation for 32bit S1 PTWs
* Add more comments to S2 PTW starting level computation

v1 -> v2:
* Fix HPFAR_EL2 access checks
* Prettify computation of starting level for S2 PTW
* Improve description of ap argument to get_S2prot
* Fix EXEC protection in get_S2prot
* Improve comments on S2 PTW attribute extraction
* Add comment describing ARMMMUFaultInfo

Edgar E. Iglesias (14):
  target-arm: Add HPFAR_EL2
  target-arm: lpae: Make t0sz and t1sz signed integers
  target-arm: lpae: Move declaration of t0sz and t1sz
  target-arm: Add support for AArch32 S2 negative t0sz
  target-arm: lpae: Replace tsz with computed inputsize
  target-arm: lpae: Rename granule_sz to stride
  target-arm: Add computation of starting level for S2 PTW
  target-arm: Add support for S2 page-table protection bits
  target-arm: Avoid inline for get_phys_addr
  target-arm: Add ARMMMUFaultInfo
  target-arm: Add S2 translation to 64bit S1 PTWs
  target-arm: Add S2 translation to 32bit S1 PTWs
  target-arm: Route S2 MMU faults to EL2
  target-arm: Add support for S1 + S2 MMU translations

 target-arm/cpu.h       |   1 +
 target-arm/helper.c    | 372 ++++++++++++++++++++++++++++++++++++++++---------
 target-arm/internals.h |  40 +++++-
 target-arm/op_helper.c |  18 ++-
 4 files changed, 359 insertions(+), 72 deletions(-)

-- 
1.9.1