From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhQu-0000cz-NL for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:03:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZqhQp-0002m4-1S for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:03:28 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:35870) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhQo-0002lf-T2 for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:03:22 -0400 Received: by pacfv9 with SMTP id fv9so196896948pac.3 for ; Mon, 26 Oct 2015 06:03:22 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 26 Oct 2015 14:02:07 +0100 Message-Id: <1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> References: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 14/14] target-arm: Add support for S1 + S2 MMU translations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 38 +++++++++++++++++++++++++++++++------- target-arm/op_helper.c | 1 + 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3857c0b..a8b8706 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7180,14 +7180,38 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUFaultInfo *fi) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - /* TODO: when we support EL2 we should here call ourselves recursively - * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw - * functions will also need changing to perform ARMMMUIdx_S2NS loads - * rather than direct physical memory loads when appropriate. - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + /* Call ourselves recursively to do the stage 1 and then stage 2 + * translations. */ - assert(!arm_feature(env, ARM_FEATURE_EL2)); - mmu_idx += ARMMMUIdx_S1NSE0; + if (arm_feature(env, ARM_FEATURE_EL2)) { + hwaddr ipa; + int s2_prot; + int ret; + + ret = get_phys_addr(env, address, access_type, + mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, + prot, page_size, fsr, fi); + + /* If S1 fails or S2 is disabled, return early. */ + if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + *phys_ptr = ipa; + return ret; + } + + /* S1 is done. Now do S2 translation. */ + ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, + phys_ptr, attrs, &s2_prot, + page_size, fsr, fi); + fi->s2addr = ipa; + /* Combine the S1 and S2 perms. */ + *prot &= s2_prot; + return ret; + } else { + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + */ + mmu_idx += ARMMMUIdx_S1NSE0; + } } /* The page table entries may downgrade secure to non-secure, but diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 333078a..a4c4ebf 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -101,6 +101,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, target_el = exception_target_el(env); if (fi.stage2) { target_el = 2; + env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; } same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */ -- 1.9.1