qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com,
	edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de
Subject: [Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2
Date: Mon, 26 Oct 2015 14:01:54 +0100	[thread overview]
Message-ID: <1445864527-14520-2-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/cpu.h    |  1 +
 target-arm/helper.c | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3daa7f5..7d3c4c7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -279,6 +279,7 @@ typedef struct CPUARMState {
             };
             uint64_t far_el[4];
         };
+        uint64_t hpfar_el2;
         union { /* Translation result. */
             struct {
                 uint64_t _unused_par_0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e7fda37..3aec303 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3230,6 +3230,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     REGINFO_SENTINEL
 };
 
@@ -3460,6 +3464,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
       .access = PL2_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
+    { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
+      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns,
+      .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
+    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+      .access = PL2_RW,
+      .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
     REGINFO_SENTINEL
 };
 
-- 
1.9.1

  reply	other threads:[~2015-10-26 13:02 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-26 13:01 [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-26 13:01 ` Edgar E. Iglesias [this message]
2015-10-26 13:01 ` [Qemu-devel] [PATCH v5 02/14] target-arm: lpae: Make t0sz and t1sz signed integers Edgar E. Iglesias
2015-10-26 13:01 ` [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz Edgar E. Iglesias
2015-10-26 13:01 ` [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz Edgar E. Iglesias
2015-10-26 13:01 ` [Qemu-devel] [PATCH v5 05/14] target-arm: lpae: Replace tsz with computed inputsize Edgar E. Iglesias
2015-10-26 13:01 ` [Qemu-devel] [PATCH v5 06/14] target-arm: lpae: Rename granule_sz to stride Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 07/14] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 08/14] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 09/14] target-arm: Avoid inline for get_phys_addr Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 10/14] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 11/14] target-arm: Add S2 translation to 64bit S1 PTWs Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit " Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-26 13:02 ` [Qemu-devel] [PATCH v5 14/14] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias
2015-10-27 14:05 ` [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5 Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1445864527-14520-2-git-send-email-edgar.iglesias@gmail.com \
    --to=edgar.iglesias@gmail.com \
    --cc=agraf@suse.de \
    --cc=alex.bennee@linaro.org \
    --cc=edgar.iglesias@xilinx.com \
    --cc=laurent.desnogues@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=serge.fdrv@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).