From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhPy-0007Qv-Ps for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZqhPu-0002Ws-Vr for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:30 -0400 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]:35792) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhPu-0002WX-Qj for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:26 -0400 Received: by pasz6 with SMTP id z6so188258973pas.2 for ; Mon, 26 Oct 2015 06:02:26 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 26 Oct 2015 14:01:56 +0100 Message-Id: <1445864527-14520-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> References: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Move declaration of t0sz and t1sz to the top of the function avoiding a mix of code and variable declarations. No functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 149a857..4d8a25a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6464,6 +6464,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUFaultType fault_type = translation_fault; uint32_t level = 1; uint32_t epd = 0; + int32_t t0sz, t1sz; int32_t tsz; uint32_t tg; uint64_t ttbr; @@ -6519,12 +6520,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - int32_t t0sz = extract32(tcr->raw_tcr, 0, 6); + t0sz = extract32(tcr->raw_tcr, 0, 6); if (va_size == 64) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } - int32_t t1sz = extract32(tcr->raw_tcr, 16, 6); + t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16); -- 1.9.1