From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhQ6-0007ce-By for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZqhQ0-0002YW-Ny for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:38 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:33129) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqhQ0-0002YQ-Hu for qemu-devel@nongnu.org; Mon, 26 Oct 2015 09:02:32 -0400 Received: by pacfa8 with SMTP id fa8so9283922pac.0 for ; Mon, 26 Oct 2015 06:02:32 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 26 Oct 2015 14:01:57 +0100 Message-Id: <1445864527-14520-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> References: <1445864527-14520-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Add support for AArch32 S2 negative t0sz. In preparation for using 40bit IPAs on AArch32. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4d8a25a..5e3d21e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6520,10 +6520,26 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - t0sz = extract32(tcr->raw_tcr, 0, 6); if (va_size == 64) { + /* AArch64 translation. */ + t0sz = extract32(tcr->raw_tcr, 0, 6); t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); + } else if (mmu_idx != ARMMMUIdx_S2NS) { + /* AArch32 stage 1 translation. */ + t0sz = extract32(tcr->raw_tcr, 0, 3); + } else { + /* AArch32 stage 2 translation. */ + bool sext = extract32(tcr->raw_tcr, 4, 1); + bool sign = extract32(tcr->raw_tcr, 3, 1); + t0sz = sextract32(tcr->raw_tcr, 0, 4); + + /* If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n"); + } } t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { -- 1.9.1