qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Christopher Covington <cov@codeaurora.org>
To: drjones@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org,
	kvmarm@lists.cs.columbia.edu, wei@redhat.com
Cc: alindsay@codeaurora.org, croberts@codeaurora.org,
	Christopher Covington <cov@codeaurora.org>,
	shannon.zhao@linaro.org, alistair.francis@xilinx.com
Subject: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases
Date: Mon, 26 Oct 2015 11:38:49 -0400	[thread overview]
Message-ID: <1445873930-9058-3-git-send-email-cov@codeaurora.org> (raw)
In-Reply-To: <1445873930-9058-1-git-send-email-cov@codeaurora.org>

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.

Signed-off-by: Christopher Covington <cov@codeaurora.org>
---
 arm/pmu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arm/pmu.c b/arm/pmu.c
index 42d0ee1..c44d708 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -14,6 +14,8 @@
  */
 #include "libcflat.h"
 
+#define NR_SAMPLES 10
+
 #if defined(__arm__)
 static inline uint32_t get_pmcr(void)
 {
@@ -22,6 +24,25 @@ static inline uint32_t get_pmcr(void)
 	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
 	return ret;
 }
+
+static inline void set_pmcr(uint32_t pmcr)
+{
+	asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (pmcr));
+}
+
+/*
+ * While PMCCNTR can be accessed as a 64 bit coprocessor register, returning 64
+ * bits doesn't seem worth the trouble when differential usage of the result is
+ * expected (with differences that can easily fit in 32 bits). So just return
+ * the lower 32 bits of the cycle count in AArch32.
+ */
+static inline unsigned long get_pmccntr(void)
+{
+	unsigned long cycles;
+
+	asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles));
+	return cycles;
+}
 #elif defined(__aarch64__)
 static inline uint32_t get_pmcr(void)
 {
@@ -30,6 +51,19 @@ static inline uint32_t get_pmcr(void)
 	asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
 	return ret;
 }
+
+static inline void set_pmcr(uint32_t pmcr)
+{
+	asm volatile("msr pmcr_el0, %0" : : "r" (pmcr));
+}
+
+static inline unsigned long get_pmccntr(void)
+{
+	unsigned long cycles;
+
+	asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles));
+	return cycles;
+}
 #endif
 
 struct pmu_data {
@@ -72,11 +106,37 @@ static bool check_pmcr(void)
 	return pmu.implementer != 0;
 }
 
+/*
+ * Ensure that the cycle counter progresses between back-to-back reads.
+ */
+static bool check_cycles_increase(void)
+{
+	struct pmu_data pmu = { {0} };
+
+	pmu.enable = 1;
+	set_pmcr(pmu.pmcr_el0);
+
+	for (int i = 0; i < NR_SAMPLES; i++) {
+		unsigned long a, b;
+
+		a = get_pmccntr();
+		b = get_pmccntr();
+
+		if (a >= b) {
+			printf("Read %ld then %ld.\n", a, b);
+			return false;
+		}
+	}
+
+	return true;
+}
+
 int main(void)
 {
 	report_prefix_push("pmu");
 
 	report("Control register", check_pmcr());
+	report("Monotonically increasing cycle count", check_cycles_increase());
 
 	return report_summary();
 }
-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

  parent reply	other threads:[~2015-10-26 15:39 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-01 19:47 [Qemu-devel] [PATCH] arm: Add PMU test Christopher Covington
2015-10-02  9:58 ` Andrew Jones
2015-10-02 15:48 ` [Qemu-devel] [kvm-unit-tests PATCHv2] " Christopher Covington
2015-10-05 21:37   ` Wei Huang
2015-10-06 17:49     ` [Qemu-devel] [kvm-unit-tests PATCHv3] ARM PMU tests Christopher Covington
2015-10-06 17:49       ` [Qemu-devel] [kvm-unit-tests PATCHv3 1/3] arm: Add PMU test Christopher Covington
2015-10-06 19:38         ` Andrew Jones
2015-10-06 17:49       ` [Qemu-devel] [kvm-unit-tests PATCHv3 2/3] arm: pmu: Check cycle count increases Christopher Covington
2015-10-06 19:49         ` Andrew Jones
2015-10-06 17:49       ` [Qemu-devel] [kvm-unit-tests PATCHv3 3/3] arm: pmu: Add CPI checking Christopher Covington
2015-10-06 20:14         ` Andrew Jones
2015-10-12 15:07     ` [Qemu-devel] [kvm-unit-tests PATCHv4] ARM PMU tests Christopher Covington
2015-10-12 15:07       ` [Qemu-devel] [kvm-unit-tests PATCHv4 1/3] arm: Add PMU test Christopher Covington
2015-10-18 17:54         ` Andrew Jones
2015-10-12 15:07       ` [Qemu-devel] [kvm-unit-tests PATCHv4 2/3] arm: pmu: Check cycle count increases Christopher Covington
2015-10-18 18:10         ` Andrew Jones
2015-10-12 15:07       ` [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking Christopher Covington
2015-10-18 18:28         ` Andrew Jones
2015-10-19 15:44           ` Christopher Covington
2015-10-26 12:25             ` Andrew Jones
2015-10-18 18:29       ` [Qemu-devel] [kvm-unit-tests PATCHv4] ARM PMU tests Andrew Jones
2015-10-26 15:38       ` [Qemu-devel] [kvm-unit-tests PATCHv5] " Christopher Covington
2015-10-26 15:38         ` [Qemu-devel] [kvm-unit-tests PATCHv5 1/3] arm: Add PMU test Christopher Covington
2015-10-26 15:38         ` Christopher Covington [this message]
2015-10-26 15:58           ` [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases Andrew Jones
2015-10-26 16:04             ` Christopher Covington
2015-10-26 16:04             ` Andrew Jones
2015-10-26 15:38         ` [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking Christopher Covington
2015-10-26 16:28           ` Andrew Jones
2015-10-28 19:12       ` [Qemu-devel] [kvm-unit-tests PATCHv6] ARM PMU tests Christopher Covington
2015-10-28 19:12         ` [Qemu-devel] [kvm-unit-tests PATCHv5 1/3] arm: Add PMU test Christopher Covington
2015-10-28 19:12         ` [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases Christopher Covington
2015-10-28 19:12         ` [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking Christopher Covington
2015-10-30 13:00           ` Andrew Jones
2015-10-30 19:32             ` Christopher Covington
2015-11-02 15:58               ` Andrew Jones
2015-11-11  2:05                 ` Andrew Jones
2015-11-11 12:50                   ` Christopher Covington

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1445873930-9058-3-git-send-email-cov@codeaurora.org \
    --to=cov@codeaurora.org \
    --cc=alindsay@codeaurora.org \
    --cc=alistair.francis@xilinx.com \
    --cc=croberts@codeaurora.org \
    --cc=drjones@redhat.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=qemu-devel@nongnu.org \
    --cc=shannon.zhao@linaro.org \
    --cc=wei@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).