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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/27] i.MX: Standardize i.MX AVIC debug
Date: Tue, 27 Oct 2015 14:33:11 +0000	[thread overview]
Message-ID: <1445956409-1818-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org>

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 29885ffea2577eaf2288c1d17fd87ee951748b49.1445781957.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/imx_avic.c | 44 ++++++++++++++++++--------------------------
 1 file changed, 18 insertions(+), 26 deletions(-)

diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c
index 96c376b..e0535ff 100644
--- a/hw/intc/imx_avic.c
+++ b/hw/intc/imx_avic.c
@@ -17,27 +17,17 @@
 
 #include "hw/intc/imx_avic.h"
 
-#define DEBUG_INT 1
-#undef DEBUG_INT /* comment out for debugging */
-
-#ifdef DEBUG_INT
-#define DPRINTF(fmt, args...) \
-do { printf("%s: " fmt , TYPE_IMX_AVIC, ##args); } while (0)
-#else
-#define DPRINTF(fmt, args...) do {} while (0)
+#ifndef DEBUG_IMX_AVIC
+#define DEBUG_IMX_AVIC 0
 #endif
 
-/*
- * Define to 1 for messages about attempts to
- * access unimplemented registers or similar.
- */
-#define DEBUG_IMPLEMENTATION 1
-#if DEBUG_IMPLEMENTATION
-#  define IPRINTF(fmt, args...) \
-    do  { fprintf(stderr, "%s: " fmt, TYPE_IMX_AVIC, ##args); } while (0)
-#else
-#  define IPRINTF(fmt, args...) do {} while (0)
-#endif
+#define DPRINTF(fmt, args...) \
+    do { \
+        if (DEBUG_IMX_AVIC) { \
+            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_AVIC, \
+                                             __func__, ##args); \
+        } \
+    } while (0)
 
 static const VMStateDescription vmstate_imx_avic = {
     .name = TYPE_IMX_AVIC,
@@ -115,8 +105,8 @@ static uint64_t imx_avic_read(void *opaque,
 {
     IMXAVICState *s = (IMXAVICState *)opaque;
 
+    DPRINTF("read(offset = 0x%" HWADDR_PRIx ")\n", offset);
 
-    DPRINTF("read(offset = 0x%x)\n", offset >> 2);
     switch (offset >> 2) {
     case 0: /* INTCNTL */
         return s->intcntl;
@@ -213,7 +203,8 @@ static uint64_t imx_avic_read(void *opaque,
         return 0x4;
 
     default:
-        IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_IMX_AVIC, __func__, offset);
         return 0;
     }
 }
@@ -225,13 +216,13 @@ static void imx_avic_write(void *opaque, hwaddr offset,
 
     /* Vector Registers not yet supported */
     if (offset >= 0x100 && offset <= 0x2fc) {
-        IPRINTF("%s to vector register %d ignored\n", __func__,
-                (unsigned int)((offset - 0x100) >> 2));
+        qemu_log_mask(LOG_UNIMP, "[%s]%s: vector %d ignored\n",
+                      TYPE_IMX_AVIC, __func__, (int)((offset - 0x100) >> 2));
         return;
     }
 
-    DPRINTF("%s(0x%x) = %x\n", __func__,
-            (unsigned int)offset>>2, (unsigned int)val);
+    DPRINTF("(0x%" HWADDR_PRIx ") = 0x%x\n", offset, (unsigned int)val);
+
     switch (offset >> 2) {
     case 0: /* Interrupt Control Register, INTCNTL */
         s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM);
@@ -305,7 +296,8 @@ static void imx_avic_write(void *opaque, hwaddr offset,
         return;
 
     default:
-        IPRINTF("%s: Bad offset %x\n", __func__, (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_IMX_AVIC, __func__, offset);
     }
     imx_avic_update(s);
 }
-- 
1.9.1

  parent reply	other threads:[~2015-10-27 14:33 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-27 14:33 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked() Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 02/27] target-arm/translate.c: Handle non-executable page-straddling Thumb insns Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 08/27] i.MX: Standardize i.MX I2C debug Peter Maydell
2015-10-27 14:33 ` Peter Maydell [this message]
2015-10-27 14:33 ` [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 11/27] i.MX: Standardize i.MX FEC debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 14/27] target-arm: Add HPFAR_EL2 Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 17/27] target-arm: Add support for AArch32 S2 negative t0sz Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 19/27] target-arm: lpae: Rename granule_sz to stride Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 23/27] target-arm: Add ARMMMUFaultInfo Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 25/27] target-arm: Add S2 translation to 32bit " Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 26/27] target-arm: Route S2 MMU faults to EL2 Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations Peter Maydell
2015-10-27 15:57 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-10-27 16:00   ` Peter Maydell

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