From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug
Date: Tue, 27 Oct 2015 14:33:12 +0000 [thread overview]
Message-ID: <1445956409-1818-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org>
From: Jean-Christophe Dubois <jcd@tribudubois.net>
The goal is to have debug code always compiled during build.
We standardize all debug output on the following format:
[QOM_TYPE_NAME]reporting_function: debug message
The qemu_log_mask() output is following the same format as the
above debug.
Adding some missing qemu_log_mask call for bad registers.
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 293e08f31cbb4df84d58f693243e61e770c73b3a.1445781957.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/imx_ccm.c | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
index 2e19dbb..4cc2bbc 100644
--- a/hw/misc/imx_ccm.c
+++ b/hw/misc/imx_ccm.c
@@ -16,14 +16,18 @@
#define CKIH_FREQ 26000000 /* 26MHz crystal input */
#define CKIL_FREQ 32768 /* nominal 32khz clock */
-//#define DEBUG_CCM 1
-#ifdef DEBUG_CCM
-#define DPRINTF(fmt, args...) \
-do { printf("%s: " fmt , TYPE_IMX_CCM, ##args); } while (0)
-#else
-#define DPRINTF(fmt, args...) do {} while (0)
+#ifndef DEBUG_IMX_CCM
+#define DEBUG_IMX_CCM 0
#endif
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_IMX_CCM) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_CCM, \
+ __func__, ##args); \
+ } \
+ } while (0)
+
static int imx_ccm_post_load(void *opaque, int version_id);
static const VMStateDescription vmstate_imx_ccm = {
@@ -109,7 +113,7 @@ static void update_clocks(IMXCCMState *s)
s->hsp_clk_freq = s->mcu_clk_freq / (1 + EXTRACT(s->pdr0, HSP));
s->ipg_clk_freq = s->hsp_clk_freq / (1 + EXTRACT(s->pdr0, IPG));
- DPRINTF("%s: mcu %uMHz, HSP %uMHz, IPG %uHz\n", __func__,
+ DPRINTF("mcu %uMHz, HSP %uMHz, IPG %uHz\n",
s->mcu_clk_freq / 1000000,
s->hsp_clk_freq / 1000000,
s->ipg_clk_freq);
@@ -135,7 +139,8 @@ static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
{
IMXCCMState *s = (IMXCCMState *)opaque;
- DPRINTF("%s(offset=%x)", __func__, offset >> 2);
+ DPRINTF("(offset=0x%" HWADDR_PRIx ")\n", offset);
+
switch (offset >> 2) {
case 0: /* CCMR */
DPRINTF(" ccmr = 0x%x\n", s->ccmr);
@@ -166,9 +171,11 @@ static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
case 23:
DPRINTF(" pcmr0 = 0x%x\n", s->pmcr0);
return s->pmcr0;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
+ return 0;
}
- DPRINTF(" return 0\n");
- return 0;
}
static void imx_ccm_write(void *opaque, hwaddr offset,
@@ -176,8 +183,9 @@ static void imx_ccm_write(void *opaque, hwaddr offset,
{
IMXCCMState *s = (IMXCCMState *)opaque;
- DPRINTF("%s(offset=%x, value = %x)\n", __func__,
- offset >> 2, (unsigned int)value);
+ DPRINTF("(offset=0x%" HWADDR_PRIx ", value = 0x%x)\n",
+ offset, (unsigned int)value);
+
switch (offset >> 2) {
case 0:
s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
@@ -205,6 +213,8 @@ static void imx_ccm_write(void *opaque, hwaddr offset,
return;
default:
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_CCM, __func__, offset);
return;
}
update_clocks(s);
--
1.9.1
next prev parent reply other threads:[~2015-10-27 14:33 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-27 14:33 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked() Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 02/27] target-arm/translate.c: Handle non-executable page-straddling Thumb insns Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 08/27] i.MX: Standardize i.MX I2C debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 09/27] i.MX: Standardize i.MX AVIC debug Peter Maydell
2015-10-27 14:33 ` Peter Maydell [this message]
2015-10-27 14:33 ` [Qemu-devel] [PULL 11/27] i.MX: Standardize i.MX FEC debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 14/27] target-arm: Add HPFAR_EL2 Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 17/27] target-arm: Add support for AArch32 S2 negative t0sz Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 19/27] target-arm: lpae: Rename granule_sz to stride Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 23/27] target-arm: Add ARMMMUFaultInfo Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 25/27] target-arm: Add S2 translation to 32bit " Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 26/27] target-arm: Route S2 MMU faults to EL2 Peter Maydell
2015-10-27 14:33 ` [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations Peter Maydell
2015-10-27 15:57 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-10-27 16:00 ` Peter Maydell
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