From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jc-0001UV-Jn for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zr5Jb-0007TI-GO for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:32 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jb-0007Sy-9x for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:31 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Zr5Ja-0000Vs-TY for qemu-devel@nongnu.org; Tue, 27 Oct 2015 14:33:30 +0000 From: Peter Maydell Date: Tue, 27 Oct 2015 14:33:28 +0000 Message-Id: <1445956409-1818-27-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> References: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 26/27] target-arm: Route S2 MMU faults to EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Message-id: 1445864527-14520-14-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/op_helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 36dac27..333078a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -90,13 +90,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t syn, exc; - bool same_el = (arm_current_el(env) != 0); + unsigned int target_el; + bool same_el; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } + target_el = exception_target_el(env); + if (fi.stage2) { + target_el = 2; + } + same_el = arm_current_el(env) == target_el; /* AArch64 syndrome does not have an LPAE bit */ syn = fsr & ~(1 << 9); @@ -116,7 +122,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, env->exception.vaddress = addr; env->exception.fsr = fsr; - raise_exception(env, exc, syn, exception_target_el(env)); + raise_exception(env, exc, syn, target_el); } } #endif -- 1.9.1