From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zroz3-0003cz-9z for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:19:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zroz2-0005lB-CS for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:19:21 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:10263) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zroz2-0005kt-79 for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:19:20 -0400 From: Yongbok Kim Date: Thu, 29 Oct 2015 15:18:38 +0000 Message-ID: <1446131919-36668-2-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1446131919-36668-1-git-send-email-yongbok.kim@imgtec.com> References: <1446131919-36668-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2] target-mips: add SIGRIE instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: leon.alrae@imgtec.com, aurelien@aurel32.net Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and microMIPS. The instruction allows to use the 16-bit code field for software use. This instruction is introduced by and required as of Release 6. Signed-off-by: Yongbok Kim --- target-mips/translate.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 4cb77de..df24d6b 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -323,6 +323,7 @@ enum { OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, OPC_TEQI = (0x0C << 16) | OPC_REGIMM, OPC_TNEI = (0x0E << 16) | OPC_REGIMM, + OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, OPC_DAHI = (0x06 << 16) | OPC_REGIMM, @@ -12014,7 +12015,8 @@ enum { LSA = 0x0f, ALIGN = 0x1f, EXT = 0x2c, - POOL32AXF = 0x3c + POOL32AXF = 0x3c, + SIGRIE = 0x3f }; /* POOL32AXF encoding of minor opcode field extension */ @@ -13633,6 +13635,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case BREAK32: generate_exception_end(ctx, EXCP_BREAK); break; + case SIGRIE: + check_insn(ctx, ISA_MIPS32R6); + generate_exception_end(ctx, EXCP_RI); + break; default: pool32a_invalid: MIPS_INVAL("pool32a"); @@ -18951,6 +18957,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); gen_trap(ctx, op1, rs, -1, imm); break; + case OPC_SIGRIE: + check_insn(ctx, ISA_MIPS32R6); + generate_exception_end(ctx, EXCP_RI); + break; case OPC_SYNCI: check_insn(ctx, ISA_MIPS32R2); /* Break the TB to be able to sync copied instructions -- 1.7.1