[Qemu-devel] [PULL 0/9] target-mips queue

[Leon Alrae <leon.alrae@imgtec.com>]

Hi,

Here's my current target-mips queue, just fixes and relatively minor
improvements.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 7bc8e0c967a4ef77657174d28af775691e18b4ce:

  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2015-10-29 09:49:52 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20151030

for you to fetch changes up to 60270f85cc93d2d34e45b7679c374b1d771f0eeb:

  target-mips: fix updating XContext on mmu exception (2015-10-30 14:36:19 +0000)

----------------------------------------------------------------
MIPS patches 2015-10-30

Changes:
* R6 CPU can be woken up by non-enabled interrupts
* PC fix in KVM
* CP0 XContext calculation fix
* various MIPS R6 updates

----------------------------------------------------------------
James Hogan (1):
      hw/mips_malta: Fix KVM PC initialisation

Leon Alrae (3):
      target-mips: move the test for enabled interrupts to a separate function
      target-mips: implement the CPU wake-up on non-enabled interrupts in R6
      target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

Yongbok Kim (5):
      target-mips: Add enum for BREAK32
      target-mips: add PC, XNP reg numbers to RDHWR
      target-mips: Set Config5.XNP for R6 cores
      target-mips: add SIGRIE instruction
      target-mips: fix updating XContext on mmu exception

 hw/mips/mips_malta.c         |  2 +-
 target-mips/cpu.c            |  9 ++++---
 target-mips/cpu.h            | 37 ++++++++++++++-----------
 target-mips/helper.c         | 10 ++++---
 target-mips/helper.h         |  2 ++
 target-mips/op_helper.c      | 64 ++++++++++++++++++++++++--------------------
 target-mips/translate.c      | 43 +++++++++++++++++++++++++----
 target-mips/translate_init.c |  4 +--
 8 files changed, 112 insertions(+), 59 deletions(-)