From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBB7-00080y-5Y for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsBB2-0001he-MH for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:17 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:8359) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBB2-0001hP-Dj for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:12 -0400 From: Leon Alrae Date: Fri, 30 Oct 2015 15:00:43 +0000 Message-ID: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 0/9] target-mips queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Aurelien Jarno Hi, Here's my current target-mips queue, just fixes and relatively minor improvements. Thanks, Leon Cc: Peter Maydell Cc: Aurelien Jarno The following changes since commit 7bc8e0c967a4ef77657174d28af775691e18b4ce: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2015-10-29 09:49:52 +0000) are available in the git repository at: git://github.com/lalrae/qemu.git tags/mips-20151030 for you to fetch changes up to 60270f85cc93d2d34e45b7679c374b1d771f0eeb: target-mips: fix updating XContext on mmu exception (2015-10-30 14:36:19 +0000) ---------------------------------------------------------------- MIPS patches 2015-10-30 Changes: * R6 CPU can be woken up by non-enabled interrupts * PC fix in KVM * CP0 XContext calculation fix * various MIPS R6 updates ---------------------------------------------------------------- James Hogan (1): hw/mips_malta: Fix KVM PC initialisation Leon Alrae (3): target-mips: move the test for enabled interrupts to a separate function target-mips: implement the CPU wake-up on non-enabled interrupts in R6 target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 Yongbok Kim (5): target-mips: Add enum for BREAK32 target-mips: add PC, XNP reg numbers to RDHWR target-mips: Set Config5.XNP for R6 cores target-mips: add SIGRIE instruction target-mips: fix updating XContext on mmu exception hw/mips/mips_malta.c | 2 +- target-mips/cpu.c | 9 ++++--- target-mips/cpu.h | 37 ++++++++++++++----------- target-mips/helper.c | 10 ++++--- target-mips/helper.h | 2 ++ target-mips/op_helper.c | 64 ++++++++++++++++++++++++-------------------- target-mips/translate.c | 43 +++++++++++++++++++++++++---- target-mips/translate_init.c | 4 +-- 8 files changed, 112 insertions(+), 59 deletions(-)