From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBJ-00088y-Dt for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsBBI-0001mk-Li for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:29 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:45028) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBI-0001mf-H1 for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:28 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 2E860BEC1E4FE for ; Fri, 30 Oct 2015 15:01:25 +0000 (GMT) From: Leon Alrae Date: Fri, 30 Oct 2015 15:00:45 +0000 Message-ID: <1446217252-3637-3-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> References: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org In Release 6, the behaviour of WAIT has been modified to make it a requirement that a processor that has disabled operation as a result of executing a WAIT will resume operation on arrival of an interrupt even if interrupts are not enabled. Signed-off-by: Leon Alrae --- target-mips/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target-mips/cpu.c b/target-mips/cpu.c index bbfee45..639a24b 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -53,12 +53,13 @@ static bool mips_cpu_has_work(CPUState *cs) CPUMIPSState *env = &cpu->env; bool has_work = false; - /* It is implementation dependent if non-enabled interrupts - wake-up the CPU, however most of the implementations only + /* Prior to MIPS Release 6 it is implementation dependent if non-enabled + interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { - if (cpu_mips_hw_interrupts_enabled(env)) { + if (cpu_mips_hw_interrupts_enabled(env) || + (env->insn_flags & ISA_MIPS32R6)) { has_work = true; } } -- 2.1.0