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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Subject: [Qemu-devel] [PULL 4/9] target-mips: Add enum for BREAK32
Date: Fri, 30 Oct 2015 15:00:47 +0000	[thread overview]
Message-ID: <1446217252-3637-5-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com>

From: Yongbok Kim <yongbok.kim@imgtec.com>

Add enum for BREAK32

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a10bfa3..3105c7f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12009,6 +12009,7 @@ enum {
     MODU = 0x7,
 
     /* The following can be distinguished by their lower 6 bits. */
+    BREAK32 = 0x07,
     INS = 0x0c,
     LSA = 0x0f,
     ALIGN = 0x1f,
@@ -13629,7 +13630,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case POOL32AXF:
             gen_pool32axf(env, ctx, rt, rs);
             break;
-        case 0x07:
+        case BREAK32:
             generate_exception_end(ctx, EXCP_BREAK);
             break;
         default:
-- 
2.1.0

  parent reply	other threads:[~2015-10-30 15:01 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-30 15:00 [Qemu-devel] [PULL 0/9] target-mips queue Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6 Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 Leon Alrae
2015-10-30 15:00 ` Leon Alrae [this message]
2015-10-30 15:00 ` [Qemu-devel] [PULL 5/9] hw/mips_malta: Fix KVM PC initialisation Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 6/9] target-mips: add PC, XNP reg numbers to RDHWR Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 7/9] target-mips: Set Config5.XNP for R6 cores Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction Leon Alrae
2015-10-30 15:00 ` [Qemu-devel] [PULL 9/9] target-mips: fix updating XContext on mmu exception Leon Alrae
2015-10-30 17:36 ` [Qemu-devel] [PULL 0/9] target-mips queue Peter Maydell

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