From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsGXn-0003j0-S0 for qemu-devel@nongnu.org; Fri, 30 Oct 2015 16:45:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsGXj-0003ip-S3 for qemu-devel@nongnu.org; Fri, 30 Oct 2015 16:45:03 -0400 Received: from mail-qg0-x229.google.com ([2607:f8b0:400d:c04::229]:34421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsGXj-0003iY-OP for qemu-devel@nongnu.org; Fri, 30 Oct 2015 16:44:59 -0400 Received: by qgem9 with SMTP id m9so71642244qge.1 for ; Fri, 30 Oct 2015 13:44:59 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 30 Oct 2015 13:44:24 -0700 Message-Id: <1446237864-11912-2-git-send-email-rth@twiddle.net> In-Reply-To: <1446237864-11912-1-git-send-email-rth@twiddle.net> References: <1446237864-11912-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL] target-tilegx: Implement prefetch instructions in pipe y2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Chen Gang , xili_gchen_5257@hotmail.com From: Chen Gang Originally, tilegx qemu only implement prefetch instructions in pipe x1, did not implement them in pipe y2. Signed-off-by: Chen Gang Signed-off-by: Richard Henderson --- target-tilegx/translate.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 34d45f8..354f25a 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2105,38 +2105,44 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) unsigned srcbdest = get_SrcBDest_Y2(bundle); const char *mnemonic; TCGMemOp memop; + bool prefetch_nofault = false; switch (OEY2(opc, mode)) { case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_SB; - mnemonic = "ld1s"; + mnemonic = "ld1s"; /* prefetch_l1_fault */ goto do_load; case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_UB; - mnemonic = "ld1u"; + mnemonic = "ld1u"; /* prefetch, prefetch_l1 */ + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_TESW; - mnemonic = "ld2s"; + mnemonic = "ld2s"; /* prefetch_l2_fault */ goto do_load; case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_TEUW; - mnemonic = "ld2u"; + mnemonic = "ld2u"; /* prefetch_l2 */ + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TESL; - mnemonic = "ld4s"; + mnemonic = "ld4s"; /* prefetch_l3_fault */ goto do_load; case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TEUL; - mnemonic = "ld4u"; + mnemonic = "ld4u"; /* prefetch_l3 */ + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TEQ; mnemonic = "ld"; do_load: - tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), - dc->mmuidx, memop); + if (!prefetch_nofault) { + tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), + dc->mmuidx, memop); + } qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, reg_names[srcbdest], reg_names[srca]); return TILEGX_EXCP_NONE; -- 2.4.3