From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtJGS-00074e-GE for qemu-devel@nongnu.org; Mon, 02 Nov 2015 12:51:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZtJGP-0004qr-75 for qemu-devel@nongnu.org; Mon, 02 Nov 2015 12:51:28 -0500 Received: from mail-lf0-x234.google.com ([2a00:1450:4010:c07::234]:35412) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtJGP-0004qm-0E for qemu-devel@nongnu.org; Mon, 02 Nov 2015 12:51:25 -0500 Received: by lfbn126 with SMTP id n126so64925622lfb.2 for ; Mon, 02 Nov 2015 09:51:24 -0800 (PST) From: Sergey Fedorov Date: Mon, 2 Nov 2015 20:51:08 +0300 Message-Id: <1446486668-2133-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH] target-arm: Fix arm_debug_excp_handler() for singlestep enabled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Sergey Fedorov , Peter Maydell CPU singlestep is done by generating a debug internal exception. Do not raise a real CPU exception in case of singlestepping. Signed-off-by: Sergey Fedorov --- target-arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 7929c71..67d9ffb 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -909,7 +909,7 @@ void arm_debug_excp_handler(CPUState *cs) uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); - if (cpu_breakpoint_test(cs, pc, BP_GDB)) { + if (cs->singlestep_enabled || cpu_breakpoint_test(cs, pc, BP_GDB)) { return; } -- 1.9.1